RT5510WSC datasheet(17/52 Pages) RICHTEK

17 / 52 page

RT5510

is a registered trademark of Richtek Technology Corporation

DS5510-00

October

2019

www.richtek.com

Mode Transition

The state machine of mode transition is shown in Figure 7. After power on, the control bit will always be reset to

PWDN mode.

PWDN

FAULT

DVDD, VBAT valid = 1

PWDN = 0 (I

SR valid = 1 & BCK valid = 1

PWDN = 1 (I

OTP/OCP/OVP/UVP = 1

OTP/OCP/OVP/UVP = 0

(Check every 200ms)

PWDN = 1 (I

SUSP

SR valid = 0 or BCK valid = 0

PWDN = 1 (I

Figure 7. Mode Transition

Power ON/OFF Sequence

The power on sequence is shown in Figure 8. After power is valid, two groups of control signals should be set.

I2C : PWDN and AMPE should be programmed. These two bits can be programmed by single command since they

are at the same byte address.

I2S : BCK should be valid on the specified interface.

If the PWDN is set to 0 before the BCK is valid, it will go to SUSP mode automatically. The output of amplifier will be

valid after entering OP mode Signal ramp up will always be implemented when the mode transits from PWDN or

SUSP mode to OP mode.

DVDD, VBAT

PWDN (I

BCK (I

(SUSP)

Power on

DATA Output (I

Operation

INITIAL (I

6ms

Amp on (I

1ms

Amp off

Amp off (I

2C)

(SUSP)

power off

Figure 8. Power ON/OFF Sequence

RT5510WSC Datasheet(PDF) 17 Page - Richtek Technology Corporation

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