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RT5510WSC Datasheet(PDF) 18 Page - Richtek Technology Corporation |
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RT5510WSC Datasheet(HTML) 18 Page - Richtek Technology Corporation |
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18 / 52 page ![]() RT5510 Copyright © 2019 Richtek Technology Corporation. All rights reserved. is a registered trademark of Richtek Technology Corporation www.richtek.com DS5510-00 October 2019 18 I 2S Mode Change without PWDN When I2S mode change, like BCK and LRCK frequency relationship, the chip will not be shut down. If the clock source from I2S changes, I2S invalid is detected. In this case, soft muting is implemented before entering Amp off situation. In the opposite situation, if the clock source from I2S is detected valid again, signal ramp up is implemented at the start after it enters the operating mode. The above procedure is shown in Figure 9 and ramp is setting by register 0x 28 bit [2:0]. BCK (I 2 S) BCK unstable OP Amp Output OP ramp down ramp up Amp off Figure 9. I2S Mode Change without PWDN Table 3. Ramp Control Setting Register Bits Bits Name Description 0x28 2:0 VOLCTRL Ramp control when new volume setting is different from old setting : 000 : No ramp up/down (default) 001 : 0.5db per sample 010 : 0.5db per 2 samples 011 : 0.5dB per 4 samples 100 : 0.5dB per 8 samples 101 : 0.5dB per 16 samples 110 : 0.5dB per 32 samples 111 : 0.5dB per 64 samples |
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