LM5145 datasheet(45/60 Pages) TI1

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at VIN each time the input supply is cycled ON and OFF. The parasitic resistance causes the input voltage to

dip during a load transient. If the regulator is operating close to the minimum input voltage, this dip can cause

false UVLO fault triggering and a system reset. The best way to solve such issues is to reduce the distance from

the input supply to the regulator and use an aluminum or tantalum input capacitor in parallel with the ceramics.

The moderate ESR of the electrolytic capacitors helps to damp the input resonant circuit and reduce any voltage

overshoots. A capacitance in the range of 10 µF to 47 µF is usually sufficient to provide input damping and helps

to hold the input voltage steady during large load transients.

An EMI input filter is often used in front of the regulator that, unless carefully designed, can lead to instability

as well as some of the effects mentioned above. The application report Simple Success with Conducted EMI for

DC-DC Converters provides helpful suggestions when designing an input filter for any switching regulator.

9.4 Layout

9.4.1 Layout Guidelines

Proper PCB design and layout is important in a high-current, fast-switching circuits (with high current and voltage

slew rates) to assure appropriate device operation and design robustness. As expected, certain issues must

be considered before designing a PCB layout using the LV5144. The high-frequency power loop of the buck

converter power stage is denoted by #1 in the shaded area of Figure 9-33. The topological architecture of a buck

converter means that particularly high di/dt current flows in the components of loop 1, and it becomes mandatory

to reduce the parasitic inductance of this loop by minimizing its effective loop area. Also important is the gate

drive loops of the low-side and high-side MOSFETs, denoted by 2 and 3, respectively, in Figure 9-33.

BST

VCC

PGND

VIN

VOUT

GND

LV5144

VCC

Low-side gate

driver

High-side

gate driver

CVCC

CBST

CIN

COUT

High frequency

power loop

GND

Figure 9-33. DC/DC Regulator Ground System With Power Stage and Gate Drive Circuit Switching Loops

9.4.1.1 Power Stage Layout

1. Input capacitors, output capacitors, and MOSFETs are the constituent components of the power stage of a

buck regulator and are typically placed on the top side of the PCB (solder side). The benefits of convective

heat transfer are maximized because of leveraging any system-level airflow. In a two-sided PCB layout,

small-signal components are typically placed on the bottom side (component side). insert at least one inner

plane, connected to ground, to shield and isolate the small-signal traces from noisy power traces and lines.

2. The DC/DC converter has several high-current loops. Minimize the area of these loops in order to suppress

generated switching noise and parasitic loop inductance and optimize switching performance.

• Loop #1: The most important loop to minimize the area of is the path from the input capacitor or

capacitors through the high- and low-side MOSFETs, and back to the capacitor or capacitors through the

ground connection. Connect the input capacitor or capacitors negative terminal close to the source of the

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