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KT0806L Datasheet(PDF) 2 Page - List of Unclassifed Manufacturers

Part # KT0806L
Description  Monolithic Digital Stereo FM Transmitter Radio-Station-on-a-Chip™
PDF  23 Pages
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Manufacturer  ETC [List of Unclassifed Manufacturers]
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KT0806L Datasheet(HTML) 2 Page - List of Unclassifed Manufacturers

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Copyright
©2010, KT Micro, Inc.
2
KT0806L
1 Operation Condition
Table 1: Operation Condition
Parameter
Symbol
Operating Condition
Min
Typ
Max
Units
IO/Regulator Supply
IOVDD
Relative to GND
1.6
3.6
V
Ambient Temperature
TA
-30
25
70
℃
2 Specifications and Features
Table 2: FM Transmitter Functional Parameters (Unless otherwise noted TA = -30-70 ℃,
IOVDD=1.6~3.6 V, Fin = 1 KHz)
Parameter
Symbol
Test/Operating
Condition
Min
Nom
Max
Units
FM Frequency Range
Ftx
Pin 12
70
108
MHz
Current Consumption
IVDD
Pin 16 with PA (power
amp.) at default power
mode (PA_bias = 0,
RFGAIN[3:0]=1111)
-
17
mA
Standby Current
Istand
Pin 16
-
0.1
1
μA
Signal to Noise Ratio
SNR
Vin = 1 Vp-p, Gin = 0
-
66
-
dB
Total Harmonic Distortion
THD
Vin = 1 Vp-p, Gin = 0
-
0.3
%
Left/Right Channel Balance
BAL
Vin = 1 Vp-p, Gin = 0
-0.2
-
0.2
dB
Stereo Separation (Left<->Right)
SEP
Vin = 1 Vp-p, Gin = 0
40
-
dB
Sub Carrier Rejection Ratio
SCR
Vin = 1 Vp-p, Gin = 0
-
-
60
dB
Input Swing1
Vin
Single-ended input
-
0.35
2
VRMS
PGA Range for Audio Input
Gin
-15
0
12
dB
PGA Gain Step for Audio Input
Gstep
1
4
dB
Required Input Common-Mode
Voltage when DC-coupled
Vcm
Pin 2,4
0
0.8
1.8
V
Power Supply Rejection2
PSRR
IOVDD = 1.9 ~ 3.6 V
40
-
-
dB
Ground Bounce Rejection2
GSRR
IOVDD = 1.9 ~ 3.6 V
40
-
-
dB
Input Resistance (Audio Input)
Rin
Pin 2, 4
120
150
180
kΩ
Input Capacitance (Audio Input)
Cin
Pin 2, 4
0.5
0.8
1.2
pF
Audio Input Frequency Band
Fin
Pin 2, 4
20
-
15k
Hz
Transmit Level
Vout
96
103
113
dBµV
Channel Step
STEP
-
50
KHz
Pilot Deviation
7.5
15
KHz
Audio Deviation
75
112.5
KHz
Frequency Response
Mono,-3dB, ΔF=60KHz,
50/75μs pre-emphasis
20
15,000
Hz
PHTCNST = 1
-
50
-
µs
Pre-emphasis Time Constant
Tpre
PHTCNST = 0
-
75
-
µs
Crystal/External Clock
CLK
Input clock
32.768
40,000
KHz
2-wire I2C Clock
SCL
Pin 11
0
100
400
KHz
High Level Input Voltage
VIH
Pin 7, 8, 10, 11
0.75 x
IOVDD
-
IOVDD
+ 0.25
V
Low Level Input Voltage
VIL
Pin 7, 8, 10, 11
- 0.25
-
0.25 x
IOVDD
V
Notes:
1. Maximum is given on the condition of PGA gain = -15dB.
2. Fin = 20 ~ 15KHz.



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