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KT0806L Datasheet(PDF) 4 Page - List of Unclassifed Manufacturers

Part # KT0806L
Description  Monolithic Digital Stereo FM Transmitter Radio-Station-on-a-Chip™
PDF  23 Pages
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Manufacturer  ETC [List of Unclassifed Manufacturers]
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KT0806L Datasheet(HTML) 4 Page - List of Unclassifed Manufacturers

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Copyright
©2010, KT Micro, Inc.
4
KT0806L
4 I2C Compatible 2-Wire Serial Interface
4.1 General Descriptions
The serial interface consists of a serial controller and registers. An internal address decoder transfers the
content of the data into appropriate registers. Please note that the I2C address is 0x 0110110 the same as
in KT0806. Neither software nor hardware change is needed if KT0806L is used to replace KT0806.
Both the write and read operations are supported according to the following protocol:
Write Operations:
BYTE WRITE:
The write operation is accomplished via a 3-byte sequence:
Serial address with write command
Register address
Register data
A write operation requires an 8-bit register address following the device address word and acknowledgment.
Upon receipt of this address, the KT0806L will again respond with a “0” and then clock in the 8-bit register
data. Following receipt of the 8-bit register data, the KT0806L will output a “0” and the addressing device,
such as a microcontroller, must terminate the write sequence with a stop condition (see Figure 3).
Read Operations:
RANDOM READ:
The read operation is accomplished via a 4-byte sequence:
Serial address with write command
Register address
Serial address with read command
Register data
Once the device address and register address are clocked in and acknowledged by the KT0806L, the
microcontroller must generate another start condition. The microcontroller now initiates a current address
read by sending a device address with the read/write select bit high. The KT0806L acknowledges the
device address and serially clocks out the register data. The microcontroller does not respond with a “0” but
does generate a following stop condition (see Figure 3).
RANDOM REGISTER WRITE PROCEDURE
S 0 1 1 0 1 1 0 W A
A
A P
7 bit address
register address
data
Acknowledge
Acknowledge
STOP condition
START condition
WRITE command
Acknowledge
RANDOM REGISTER READ PROCEDURE
S 0 1 1 0 1 1 0 W A
A S 0111110 R A
A P
7 bit address
register address
7 bit address
data
Acknowledge
Acknowledge
Acknowledge
START condition
WRITE command
READ condition
NO Acknowledge
STOP condition
Figure 3: Serial Interface Protocol



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