Copyright

©2010, KT Micro, Inc.

7

KT0806L

5 Register Bank

The register bank stores channel frequency codes, calibration parameters, operation status, mode and power

controls, which can be accessed by the internal digital controller, state machines and external micro

controllers through the serial interface.

All registers are 8 bits wide. Control logics are active high unless specifically noted.

Register

7

6

5

4

3

2

1

0

0x00

CHSEL[8:1]

0x01

RFGAIN[1:0]

PGA[2:0]

CHSEL[11:9]

0x02

CHSEL[0]

RFGAIN[3]

-

-

MUTE

PLTADJ

-

PHTCNST

0x04

ALC_EN

MONO

PGA_LSB[1:0]

-

-

0x0B

Standby

-

PDPA

-

-

AUTO_PA

DN

-

-

0x0C

ALC_DECAY_TIME[3:0]

ALC_ATTACK_TIME[3:0]

0x0E

-

-

-

-

-

-

PA_BIAS

-

0x0F

-

-

-

PW_OK

-

SLNCID

-

-

0x10

-

-

-

-

-

-

PGAMOD

0x12

SLNCDIS

SLNCTHL[2:0]

SLNCTHH[2:0]

SW_MOD

0x13

RFGAIN[2]

-

-

-

-

PA_CTRL

-

-

0x14

SLNCTIME[2:0]

SLNCCNTHIGH[2:0]

-

SLNCTIM

E[3]

0x15

ALCCMPGAIN[2:0]

0x16

-

-

-

SLNCCNTLOW[2:0]

0x17

-

FDEV

AU_ENHA

NCE

XTAL_SE

L

0x1E

DCLK

XTALD

REF_CLK[3:0]

0x26

ALCHOLD[2:0]

ALCHIGHTH[2:0]

0x27

ALCLOWTH[3:0]

Note 1: ONLY read/write the defined registers.

Note 2: Shaded registers are used in KT0806.

5.1 Register 0x00 (Address: 0x00, Default value: 0x5C)

Bit

7

6

5

4

3

2

1

0

KT0806L

CHSEL[8:1]

Please note that the default channel of KT0806L is 86MHz instead of 89.7MHz in KT0806

CHSEL[11:0] = Dec2Bin (Target frequency in MHz x 20),

where CHSEL[11:0] = Reg0x1[2:0]:Reg0x0[7:0]:Reg0x2[7]

5.2 Register 0x01 (Address: 0x01, Default value: 0xC3)

Bit

7

6

5

4

3

2

1

0

KT0806L

RFGAIN[1:0]

PGA[2:0]

CHSEL[11:9]

Bits

Type

Default

Label

Description

7:6

RW

11

RFGAIN[1:0]

Transmission Range Adjustment with RFGAIN[3] in

Reg 0x02[6] and RFGAIN[2] in Reg 0x13[7] (See

Table 4 below)