TLC555CPWR datasheet(23/42 Pages) TI1

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Control Voltage (V)

0.5

1.0

1.5

2.0

2.5

3.0

3.5

4.0

4.5

5.0

0.5

1.5

2.5

3.5

D013

Control Voltage (V)

0.5

1.0

1.5

2.0

2.5

3.0

3.5

4.0

4.5

5.0

100

D014

Modulation

Input

(see Note A)

CONT

TRIG

RESET

VDD

OUT

DISCH

VDD (5 V to 15 V)

GND

THRES

Output

TLC555

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SLFS043I – SEPTEMBER 1983 – REVISED JULY 2019

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Typical Applications (continued)

The modulating signal can be direct or capacitively coupled to CONT. For direct coupling, consider the effects of

modulation source voltage and impedance on the bias of the timer.

RA = 3 kΩ

RB = 309 kΩ

C = 1 nF

Figure 22. Circuit for Pulse-Position Modulation

8.2.3.1 Design Requirements

Both DC- and AC-coupled modulation input changes the upper and lower voltage thresholds for the timing

capacitor. Both frequency and duty cycle vary with the modulation voltage. Control voltage below 1 V could result

in output glitches instead of a steady output pulse stream

8.2.3.2 Detailed Design Procedure

The nominal output frequency and duty cycle for control voltage set to 2/3 of VDD can be determined using

formulas in Astable Operation section.

8.2.3.3 Application Curves

Figure 23. Pulse-Position-Modulation Frequency

vs Control Voltage, VDD = 5 V

Figure 24. Pulse-Position-Modulation Duty Cycle

vs Control Voltage, VDD = 5 V

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