TLC555CPWR datasheet(24/42 Pages) TI1

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VDD

RESET

VDD

OUT

DISCH

GND

CONT

TRIG

THRES

0.01

CC = 14.7 F

RC = 100 k:

Out pu t C

RESET

VDD

OUT

DISCH

GND

CONT

TRIG

THRES

33 k:

0.001

0.01

CB = 4.7 PF

RB = 100 k:

Out pu t B

Out pu t A

RA = 100 k:

CA = 10 PF

0.01

0.001

33 k:

THRES

TRIG

CONT

GND

DISCH

OUT

VDD

RESET

33 k:

1N4148

TLC555

SLFS043I – SEPTEMBER 1983 – REVISED JULY 2019

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Typical Applications (continued)

8.2.4 Sequential Timer

Many applications, such as computers, require signals for initializing conditions during start-up. Other

applications, such as test equipment, require activation of test signals in sequence. These timing circuits can be

connected to provide such sequential control. The timers can be used in various combinations of astable or

monostable circuit connections, with or without modulation, for extremely flexible waveform control. Figure 25

shows a sequencer circuit with possible applications in many systems, and Figure 26 shows the output

waveforms.

NOTE: S closes momentarily at t = 0.

Figure 25. Sequential Timer Circuit

8.2.4.1 Design Requirements

The sequential timer application chains together multiple monostable timers. The joining components are the

33-kΩ resistors and 0.001-µF capacitors. The output high to low edge passes a 10-µs start pulse to the next

monostable. A diode is needed to prevent over voltage on the trigger input when on the previous output's low to

high edge.

8.2.4.2 Detailed Design Procedure

The timing resistors and capacitors can be chosen using this formula: tw = 1.1 × R × C.

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