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AD9549BCPZ Datasheet(PDF) 58 Page - Analog Devices

Part # AD9549BCPZ
Description  Dual Input Network Clock Generator/Synchronizer
PDF  78 Pages
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Manufacturer  AD [Analog Devices]
Direct Link  http://www.analog.com
Logo AD - Analog Devices

AD9549BCPZ Datasheet(HTML) 58 Page - Analog Devices

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AD9549
Preliminary Technical Data
Rev. PrA | Page 58 of 78
I/O REGISTER MAP
Table 9
Addr
(hex)
Type
1
Name
(short
description)
D7
D6
D5
D4
D3
D2
D1
D0
Default
(hex)
0000
Serial Port Configuration and Part Identification
0000
Serial
Config
SDO
Active
LSB First
(buffered)
Soft RST
Long Inst.
18
0001
Reserved
00
0002
RO
02
0003
RO
Part ID
Part ID
09
0004
Read
Buffer
Reg
00
0005
AC
Serial
Options
Register
Update
00
0010
Power Down and Reset
0010
Power
Down /
Enable
PD HSTL
Driver
Enable
CMOS
Driver
Enable
Output
Doubler
PD
SysClk
PLL
PD RefA
PD RefB
Full PD
Digital PD
00
0011
Reserved
00
0012
M, AC
History
Reset
IRQ
Reset
FPFD
Reset
CPFD
Reset
LF Reset
CCI
Reset
DDS
Reset
00
0013
M
Reset
PD Fund
DDS
S Div2
Reset
R Div2
Reset
S Div
Reset
R Div
Reset
00
0020
System Clock
0020
N-Divider
N Divider [4:0]
12
0021
Reserved
00
0022
PLL
Parameters
VCO
Auto
Range
2x Refer-
ence
VCO
Range
Charge Pump Current
[1:0]
04
0023
PFD
Divider
PFD Divider [3:0]
(relationship between SysClk and PFD clock)
05
0100
DPLL
0100
M
PLL
Control
Single
Tone
Mode
Disable
Freq.
Estimator
Enable
Freq Slew
Limiter
Loop
Polarity
Close
Loop
30
0101
00
0102
R Divider [15:0]
00
0103
R-Divider
Falling
Edge
Triggered
R Divider
/2
00



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