WM8593 datasheet(44/98 Pages) WOLFSON

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WM8593

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PP Rev 1.0 January 2007

DIGITAL AUDIO PORT PIN CONFIGURATION

The MCLK1 and DIO1 pins are defined individually as an input or an output using MCLK1_SEL[2:0]

and DIO1_SEL[2:0] respectively.

The BCLK1 and LRCLK1 pins are always defined as inputs or

outputs together using WORDCLK1_SEL[2:0].

ADDRESS

BIT

LABEL

DEFAULT

DESCRIPTION

3:1

MCLK1_

SEL[2:0]

000

MCLK1 Pin Function Select

000 = Input to WM8593

001 = Output MCLK2

010 = Output MCLK3

011 = Output MCLK4

100 = Output MCLK5

101 to 111 = Reserved

6:4

WORD

CLK1_

SEL[2:0]

000

BCLK1 and LRCLK1 Pins Function Select

000 = Inputs to WM8593

001 = Output BCLK2 and LRCLK2

010 = Output BCLK3 and LRCLK3

011 = Output BCLK4 and LRCLK4

100 = Output BCLK5 and LRCLK5

101 = Output DAC1BCLK and DAC1LRCLK

(when DAC1 is in master mode)

110 = Output DAC2BCLK and DAC2LRCLK

(when DAC2 is in master mode)

111 = Output ADCBCLK and ADCBCLK

(when ADC is master mode)

R37

AIF_MUX1

25h

9:7

DIO1_

SEL[2:0]

000

DIO1 Pin Function Select

000 = Input to WM8593

001 = Source DIO2

010 = Source DIO3

011 = Source DIO4

100 = Source DIO5

101 = Source GPIO1

110 = Source GPIO2

111 = Source ADC Data Output

Table 32 Digital Audio Port 1 Pin Configuration

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