WM8593 datasheet(45/98 Pages) WOLFSON

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WM8593

PP Rev 1.0 January 2007

The MCLK2 and DIO2 pins are defined individually as an input or an output using MCLK2_SEL[2:0]

and DIO2_SEL[2:0] respectively.

The BCLK2 and LRCLK2 pins are always defined as inputs or

outputs together using WORDCLK2_SEL[2:0].

ADDRESS

BIT

LABEL

DEFAULT

DESCRIPTION

3:1

MCLK2_

SEL[2:0]

001

MCLK2 Pin Function Select

000 = Output MCLK1

001 = Input to WM8593

010 = Output MCLK3

011 = Output MCLK4

100 = Output MCLK5

101 to 111 = Reserved

6:4

WORD

CLK2_

SEL[2:0]

001

BCLK2 and LRCLK2 Pins Function Select

000 = Output BCLK1 and LRCLK1

001 = Inputs to WM8593

010 = Output BCLK3 and LRCLK3

011 = Output BCLK4 and LRCLK4

100 = Output BCLK5 and LRCLK5

101 = Output DAC1BCLK and DAC1LRCLK

(when DAC1 is in master mode)

110 = Output DAC2BCLK and DAC2LRCLK

(when DAC2 is in master mode)

111 = Output ADCBCLK and ADCBCLK

(when ADC is master mode)

R38

AIF_MUX2

26h

9:7

DIO2_

SEL[2:0]

001

DIO2 Pin Function Select

000 = Output DIO1

001 = Input to WM8593

010 = Output DIO3

011 = Output DIO4

100 = Output DIO5

101 = Output GPIO1

110 = Output GPIO2

111 = Output ADC Data Output

Table 33 Digital Audio Port 2 Pin Configuration

WM8593 Datasheet(PDF) 45 Page - Wolfson Microelectronics plc

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