WM8593 datasheet(87/98 Pages) WOLFSON

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WM8593

PP Rev 1.0 January 2007

R42 (2Ah) – Audio Interface MUX Configuration Register 6 (AIF_MUX6)

Bit #

Read

Write

N/A

DAC1_UPD

DAC1DIN_SEL[2:1]

Default

Bit #

Read

Write

DAC1DIN_

SEL[0]

DAC1WORDCLK_SEL[2:0]

DAC1MCLK_SEL[2:0]

DAC1_

FORCE

Default

N/A = Not Applicable (no function implemented)

Function

Description

DAC1_FORCE

Force DAC1 Clocks to Change

0 = Wait until clocks are safe before switching between clock sources

1 = Force clock sources to change immediately

See Table 40 for details of use.

DAC1MCLK_SEL[2:0]

DAC1MCLK Select

000 = Use MCLK1

001 = Use MCLK2

010 = Use MCLK3

011 = Use MCLK4

100 = Use MCLK5

101 to 111 = Reserved

DAC1WORDCLK_

SEL[2:0]

DAC1BCLK and DAC1LRCLK Select

000 = Use BCLK1 and LRCLK1

001 = Use BCLK2 and LRCLK2

010 = Use BCLK3 and LRCLK3

011 = Use BCLK4 and LRCLK4

100 = Use BCLK5 and LRCLK5

101 = Output DAC1BCLK and DAC1LRCLK (when DAC1 is in master mode)

110 = Use DAC2BCLK and DAC2LRCLK (when DAC2 is in master mode)

111 = Use ADCBCLK and ADCBCLK (when ADC is master mode)

DAC1DIN_SEL[2:0]

DAC1DIN Select

000 = Use DIO1

001 = Use DIO2

010 = Use DIO3

011 = Use DIO4

100 = Use DIO5

101 = Use GPIO1

110 = Use GPIO2

111 = Use ADCDOUT

DAC1_UPD

DAC1 Clock Update

0 = Latch corresponding DAC1 clock settings into Register Map but do not update

1 = Latch corresponding DAC1 clock settings into Register Map and update all simultaneously

Figure 58 R42 – Audio Interface MUX Configuration Register 6

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