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WM8593 Datasheet(PDF) 27 Page - Wolfson Microelectronics plc |
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WM8593 Datasheet(HTML) 27 Page - Wolfson Microelectronics plc |
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27 / 98 page ![]() Product Preview WM8593 w PP Rev 1.0 January 2007 27 DSP MODE A In DSP Mode A, the MSB of channel 1 left data input is sampled on the second rising edge of bit clock following a left/right clock rising edge. Channel 1 right data then follows. The MSB of output data changes on the first falling edge of bit clock following a left/right clock transition and may be sampled on the rising edge of bit clock. The right channel data is contiguous with the left channel data. Figure 15 DSP Mode A Timing DSP MODE B In DSP Mode B, the MSB of channel 1 left data input is sampled on the first bit clock rising edge following a left/right clock rising edge. Channel 1 right data then follows. The MSB of output data changes on the same falling edge of BCLK as the low to high left/right clock transition and may be sampled on the rising edge of bit clock. The right channel data is contiguous with the left channel data. Figure 16 DSP Mode B Timing |
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