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WM8593 Datasheet(PDF) 15 Page - Wolfson Microelectronics plc |
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WM8593 Datasheet(HTML) 15 Page - Wolfson Microelectronics plc |
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15 / 98 page  Product Preview WM8593 w PP Rev 1.0 January 2007 15 CONTROL INTERFACE TIMING – 3-WIRE MODE Figure 5 Control Interface Timing – 3-Wire Serial Control Mode Test Conditions AVDD1, DVDD = 3.3V, AVDD2 = 9V, AGND1, AGND2, DGND = 0V, TA = +25˚C, Slave Mode, fs = 48kHz, ADCMCLK, DACMCLK = 256fs, 24-bit data, unless otherwise stated. PARAMETER SYMBOL MIN TYP MAX UNIT Program Register Input Information SCLK rising edge to CSB rising edge tSCS 80 ns SCLK pulse cycle time tSCY 160 ns SCLK duty cycle 40/60 60/40 % SDIN to SCLK set-up time tDSU 20 ns SDIN hold time from SCLK rising edge tDHO 40 ns SDOUT propagation delay from SCLK rising edge tDL 5 ns CSB pulse width high tCSH 40 ns CSB rising/falling to SCLK rising tCSS 40 ns Pulse width of spikes that will be suppressed tps 2 8 ns Table 5 Control Interface Timing – 3-Wire Serial Control Mode /CS SCLK SDIN t DHO t DSU tCSH t SCY t SCS LSB t CSS SDOUT t DL LSB t CSS |
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