WM8593 datasheet(18/98 Pages) WOLFSON

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WM8593

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PP Rev 1.0 January 2007

CONTROL INTERFACE

Control of the WM8593 is achieved by a 2-wire SM-bus-compliant or 3-wire SPI compliant serial

interface with readback. Software interface mode is selected using the MODE pin as shown in Table

7 below:

MODE

INTERFACE FORMAT

Low

2 wire

High

3 wire

Table 7 Control Interface Mode Selection

2-WIRE (SM-BUS COMPATIBLE) SERIAL CONTROL INTERFACE MODE

Many devices can be controlled by the same bus, and each device has a unique 7-bit address.

The controller indicates the start of data transfer with a high to low transition on SDIN while SCLK

remains high. This indicates that a device address and data will follow. All devices on the 2-wire bus

respond to the start condition and shift in the next eight bits on SDIN (7-bit address and read/write

bit, MSB first). If the device address received matches the address of the WM8593, the WM8593

responds by pulling SDIN low on the next clock pulse (ACK). If the address is not recognised, the

WM8593 returns to the idle condition and waits for a new start condition with valid address.

When the WM8593 has acknowledged a correct address, the controller sends the first byte of control

data (B23 to B16, i.e. the WM8593 register address). The WM8593 then acknowledges the first data

byte by pulling SDIN low for one SCLK pulse. The controller then sends a second byte of control data

(B15 to B8, i.e. the first 8 bits of register data), and the WM8593 acknowledges again by pulling

SDIN low for one SCLK pulse. Finally, the controller sends a third byte of control data (B7 to B0, i.e.

the final 8 bits of register data), and the WM8593 acknowledges again by pulling SDIN low for one

SCLK pulse.

The transfer of data is complete when there is a low to high transition on SDIN while SCLK is high.

After receiving a complete address and data sequence the WM8593 returns to the idle state and

waits for another start condition. If a start or stop condition is detected out of sequence at any point

during data transfer (i.e. SDIN changes while SCLK is high), the WM8593 reverts to the idle

condition.

The WM8593 device address is 34h (0110100) or 36h (0110110), selectable by control of /CS.

/CS (PIN 45)

2-WIRE BUS ADDRESS

34h (0110100)

36h (0110110)

Table 8 2-Wire Control Interface Bus Address Selection

Figure 6 2-Wire Write Protocol

AUTO-INCREMENT REGISTER WRITE

It is possible to write to multiple consecutive registers using the auto-increment feature. When

AUTO_INC is set, the register write protocol follows the method shown in Figure 7. As with normal

while SCLK remains high, and all devices on the bus receive the device address.

WM8593 Datasheet(PDF) 18 Page - Wolfson Microelectronics plc

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