WM8593 datasheet(48/98 Pages) WOLFSON

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WM8593

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PP Rev 1.0 January 2007

The MCLK5 and DIO5 pins are defined individually as an input or an output using MCLK5_SEL[2:0]

and DIO5_SEL[2:0] respectively.

The BCLK5 and LRCLK5 pins are always defined as inputs or

outputs together using WORDCLK5_SEL[2:0].

ADDRESS

BIT

LABEL

DEFAULT

DESCRIPTION

3:1

MCLK5_

SEL[2:0]

100

MCLK5 Pin Function Select

000 = Output MCLK1

001 = Output MCLK2

010 = Output MCLK3

011 = Output MCLK4

100 = Input to WM8593

101 to 111 = Reserved

6:4

WORD

CLK5_

SEL[2:0]

100

BCLK5 and LRCLK5 Pins Function Select

000 = Output BCLK1 and LRCLK1

001 = Output BCLK2 and LRCLK2

010 = Output BCLK3 and LRCLK3

011 = Output BCLK4 and LRCLK4

100 = Inputs to WM8593

101 = Output DAC1BCLK and DAC1LRCLK

(when DAC1 is in master mode)

110 = Output DAC2BCLK and DAC2LRCLK

(when DAC2 is in master mode)

111 = Output ADCBCLK and ADCBCLK

(when ADC is master mode)

R41

AIF_MUX5

29h

9:7

DIO5_

SEL[2:0]

100

DIO5 Pin Function Select

000 = Output DIO1

001 = Output DIO2

010 = Output DIO3

011 = Output DIO4

100 = Input to WM8593

101 = Output GPIO1

110 = Output GPIO2

111 = Output ADC Data Output

Table 36 Digital Audio Port 5 Pin Configuration

WM8593 Datasheet(PDF) 48 Page - Wolfson Microelectronics plc

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