WM8593 datasheet(23/98 Pages) WOLFSON

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WM8593

PP Rev 1.0 January 2007

ADDRESS

BIT

LABEL

DEFAULT

DESCRIPTION

DIV[2:0]

000 = MCLK / 4

001 = MCLK / 8

010 = 32fs

011 = 64fs

100 = 128fs

All other values of ADC_BCLKDIV[2:0] are

reserved

R15

ADC_CTRL3

0Fh

ADC_

MSTR

ADC Master Mode Select

0 = Slave mode, ADCBCLK and ADCLRCLK

are inputs to WM8593

1 = Master mode, ADCBCLK and

ADCLRCLK are outputs from WM8593

Table 11 ADC Master Mode Control

SLAVE MODE

In slave mode, the master clock to left/right clock ratio can be auto-detected or set manually by

ADDRESS

BIT

LABEL

DEFAULT

DESCRIPTION

DAC1_CTRL2

03h

2:0

DAC1_

SR[2:0]

000

DAC2_CTRL2

08h

2:0

DAC2_

SR[2:0]

000

DAC MCLK:LRCLK Ratio

000 = Auto detect

001 = 128fs

010 = 192fs

011 = 256fs

100 = 384fs

101 = 512fs

110 = 768fs

111 = 1152fs

R14

ADC_CTRL2

0Eh

2:0

ADC_

SR[2:0]

000

ADC MCLK:LRCLK Ratio

000 = Auto detect

001 = reserved

010 = reserved

011 = 256fs

100 = 384fs

101 = 512fs

110 = 768fs

111 = Reserved

Table 12 Slave Mode MCLK to LRCLK Ratio Control

DIGITAL AUDIO DATA SAMPLING RATES

In a typical digital audio system there is one central clock source producing a reference clock to

which all audio data processing is synchronised. This clock is often referred to as the audio system’s

master clock. The WM8593 uses independent master clocks for ADC and DACs. The external

master clocks can be applied directly to the ADCMCLK, DACMCLK1 and DACMCLK2 input pins. In a

system where there are a number of possible sources for the reference clock, it is recommended that

the clock source with the lowest jitter be used for the master clock to optimise the performance of the

WM8593.

WM8593 Datasheet(PDF) 23 Page - Wolfson Microelectronics plc

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