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WM8593 Datasheet(PDF) 82 Page - Wolfson Microelectronics plc |
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WM8593 Datasheet(HTML) 82 Page - Wolfson Microelectronics plc |
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82 / 98 page  WM8593 Product Preview w PP Rev 1.0 January 2007 82 R37 (25h) – Audio Interface MUX Configuration Register 1 (AIF_MUX1) Bit # 15 14 13 12 11 10 9 8 Read 0 0 0 0 0 Write N/A N/A N/A N/A N/A PORT1_UPD DIO1_SEL[2:1] Default 0 0 0 0 0 0 0 0 Bit # 7 6 5 4 3 2 1 0 Read Write DIO1_ SEL[0] WORDCLK1_SEL[2:0] MCLK1_SEL[2:0] PORT1_ FORCE Default 0 0 0 0 0 0 0 0 N/A = Not Applicable (no function implemented) Function Description PORT1_FORCE Force Port 1 Clocks to Change 0 = Wait until clocks are safe before switching between clock sources 1 = Force clock sources to change immediately See Table 40 for details of use. MCLK1_SEL[2:0] MCLK1 Pin Function Select 000 = Input to WM8593 001 = Output MCLK2 010 = Output MCLK3 011 = Output MCLK4 100 = Output MCLK5 101 to 111 = Reserved WORDCLK1_SEL[2:0] BCLK1 and LRCLK1 Pins Function Select 000 = Inputs to WM8593 001 = Source BCLK2 and LRCLK2 010 = Source BCLK3 and LRCLK3 011 = Source BCLK4 and LRCLK4 100 = Source BCLK5 and LRCLK5 101 = Source DAC1BCLK and DAC1LRCLK (when DAC1 is in master mode) 110 = Source DAC2BCLK and DAC2LRCLK (when DAC2 is in master mode) 111 = Source ADCBCLK and ADCBCLK (when ADC is master mode) DIO1_SEL[2:0] DIO1 Pin Function Select 000 = Input to WM8593 001 = Source DIO2 010 = Source DIO3 011 = Source DIO4 100 = Source DIO5 101 = Source GPIO1 110 = Source GPIO2 111 = Source ADC Data Output PORT1_UPD Port 1 Update 0 = Latch corresponding Port 1 settings into Register Map but do not update 1 = Latch corresponding Port 1 settings into Register Map and update all simultaneously Figure 53 R37 – Audio Interface MUX Configuration Register 1 |
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