ATMEGA649 datasheet(131/375 Pages) ATMEL

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ATmega329/3290/649/6490

2552H–AVR–11/06

TIMSK1 – Timer/Counter1

Interrupt Mask Register

• Bit 5 – ICIE1: Timer/Counter1, Input Capture Interrupt Enable

When this bit is written to one, and the I-flag in the Status Register is set (interrupts glo-

bally enabled), the Timer/Counter1 Input Capture interrupt is enabled. The

corresponding Interrupt Vector (See “Interrupts” on page 49.) is executed when the

ICF1 Flag, located in TIFR1, is set.

• Bit 2 – OCIE1B: Timer/Counter1, Output Compare B Match Interrupt Enable

When this bit is written to one, and the I-flag in the Status Register is set (interrupts glo-

bally enabled), the Timer/Counter1 Output Compare B Match interrupt is enabled. The

corresponding Interrupt Vector (See “Interrupts” on page 49.) is executed when the

OCF1B Flag, located in TIFR1, is set.

• Bit 1 – OCIE1A: Timer/Counter1, Output Compare A Match Interrupt Enable

When this bit is written to one, and the I-flag in the Status Register is set (interrupts glo-

bally enabled), the Timer/Counter1 Output Compare A Match interrupt is enabled. The

corresponding Interrupt Vector (See “Interrupts” on page 49.) is executed when the

OCF1A Flag, located in TIFR1, is set.

• Bit 0 – TOIE1: Timer/Counter1, Overflow Interrupt Enable

When this bit is written to one, and the I-flag in the Status Register is set (interrupts glo-

bally enabled), the Timer/Counter1 Overflow interrupt is enabled. The corresponding

Interrupt Vector (See “Interrupts” on page 49.) is executed when the TOV1 Flag, located

in TIFR1, is set.

TIFR1 – Timer/Counter1

Interrupt Flag Register

• Bit 5 – ICF1: Timer/Counter1, Input Capture Flag

This flag is set when a capture event occurs on the ICP1 pin. When the Input Capture

set when the counter reaches the TOP value.

ICF1 is automatically cleared when the Input Capture Interrupt Vector is executed. Alter-

natively, ICF1 can be cleared by writing a logic one to its bit location.

• Bit 2 – OCF1B: Timer/Counter1, Output Compare B Match Flag

This flag is set in the timer clock cycle after the counter (TCNT1) value matches the Out-

put Compare Register B (OCR1B).

Note that a Forced Output Compare (FOC1B) strobe will not set the OCF1B Flag.

OCF1B is automatically cleared when the Output Compare Match B Interrupt Vector is

executed. Alternatively, OCF1B can be cleared by writing a logic one to its bit location.

Bit

7654

(0x6F)

–

–ICIE1

–

OCIE1B

OCIE1A

TOIE1

TIMSK1

Read/Write

R/W

Initial Value

0000

Bit

7654

321

0x16 (0x36)

–

–ICF1

–

OCF1B

OCF1A

TOV1

TIFR1

Read/Write

R/W

Initial Value

0000

000

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