ATMEGA649 datasheet(133/375 Pages) ATMEL

133 / 375 page

133

ATmega329/3290/649/6490

2552H–AVR–11/06

8-bit Timer/Counter2

with PWM and

Asynchronous

Operation

Timer/Counter2 is a general purpose, single compare unit, 8-bit Timer/Counter module.

The main features are:

• Single Compare Unit Counter

• Clear Timer on Compare Match (Auto Reload)

• Glitch-free, Phase Correct Pulse Width Modulator (PWM)

• Frequency Generator

• 10-bit Clock Prescaler

• Overflow and Compare Match Interrupt Sources (TOV2 and OCF2A)

• Allows Clocking from External 32 kHz Watch Crystal Independent of the I/O Clock

Overview

A simplified block diagram of the 8-bit Timer/Counter is shown in Figure 54. For the

actual placement of I/O pins, refer to “Pinout ATmega3290/6490” on page 2. CPU

accessible I/O Registers, including I/O bits and I/O pins, are shown in bold. The device-

specific I/O Register and bit locations are listed in the “8-bit Timer/Counter Register

Description” on page 144.

Figure 54. 8-bit Timer/Counter Block Diagram

Registers

The Timer/Counter (TCNT2) and Output Compare Register (OCR2A) are 8-bit registers.

Interrupt request (shorten as Int.Req.) signals are all visible in the Timer Interrupt Flag

The Timer/Counter can be clocked internally, via the prescaler, or asynchronously

clocked from the TOSC1/2 pins, as detailed later in this section. The asynchronous

operation is controlled by the Asynchronous Status Register (ASSR). The Clock Select

logic block controls which clock source the Timer/Counter uses to increment (or decre-

Timer/Counter

TCNTn

Waveform

Generation

OCnx

= 0

Control Logic

= 0xFF

TOP

BOTTOM

count

clear

direction

TOVn

(Int.Req.)

OCnx

(Int.Req.)

Synchronization Unit

OCRnx

TCCRnx

ASSRn

Status flags

clk

I/O

clk

ASY

Synchronized Status flags

asynchronous mode

select (ASn)

TOSC1

T/C

Oscillator

TOSC2

Prescaler

clk

I/O

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