ATMEGA649 datasheet(141/375 Pages) ATMEL

141 / 375 page

141

ATmega329/3290/649/6490

2552H–AVR–11/06

Figure 60. Phase Correct PWM Mode, Timing Diagram

The Timer/Counter Overflow Flag (TOV2) is set each time the counter reaches BOT-

TOM. The Interrupt Flag can be used to generate an interrupt each time the counter

reaches the BOTTOM value.

In phase correct PWM mode, the compare unit allows generation of PWM waveforms on

the OC2A pin. Setting the COM2A1:0 bits to two will produce a non-inverted PWM. An

inverted PWM output can be generated by setting the COM2A1:0 to three (See Table 70

on page 145). The actual OC2A value will only be visible on the port pin if the data direc-

tion for the port pin is set as output. The PWM waveform is generated by clearing (or

setting) the OC2A Register at the compare match between OCR2A and TCNT2 when

the counter increments, and setting (or clearing) the OC2A Register at compare match

between OCR2A and TCNT2 when the counter decrements. The PWM frequency for

the output when using phase correct PWM can be calculated by the following equation:

The N variable represents the prescale factor (1, 8, 32, 64, 128, 256, or 1024).

The extreme values for the OCR2A Register represent special cases when generating a

PWM waveform output in the phase correct PWM mode. If the OCR2A is set equal to

BOTTOM, the output will be continuously low and if set equal to MAX the output will be

continuously high for non-inverted PWM mode. For inverted PWM the output will have

the opposite logic values.

At the very start of period 2 in Figure 60 OCn has a transition from high to low even

though there is no Compare Match. The point of this transition is to guarantee symmetry

around BOTTOM. There are two cases that give a transition without Compare Match.

•

OCR2A changes its value from MAX, like in Figure 60. When the OCR2A value is

MAX the OCn pin value is the same as the result of a down-counting compare

match. To ensure symmetry around BOTTOM the OCn value at MAX must

correspond to the result of an up-counting Compare Match.

TOVn Interrupt Flag Set

OCnx Interrupt Flag Set

TCNTn

Period

OCnx

(COMnx1:0 = 2)

(COMnx1:0 = 3)

OCRnx Update

OCnxPCPWM

clk_I/O

N 510

⋅

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