ATMEGA649 datasheet(144/375 Pages) ATMEL

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144

ATmega329/3290/649/6490

2552H–AVR–11/06

8-bit Timer/Counter

TCCR2A – Timer/Counter

Control Register A

• Bit 7 – FOC2A: Force Output Compare A

The FOC2A bit is only active when the WGM bits specify a non-PWM mode. However,

for ensuring compatibility with future devices, this bit must be set to zero when TCCR2A

is written when operating in PWM mode. When writing a logical one to the FOC2A bit,

an immediate compare match is forced on the Waveform Generation unit. The OC2A

output is changed according to its COM2A1:0 bits setting. Note that the FOC2A bit is

implemented as a strobe. Therefore it is the value present in the COM2A1:0 bits that

determines the effect of the forced compare.

A FOC2A strobe will not generate any interrupt, nor will it clear the timer in CTC mode

using OCR2A as TOP.

The FOC2A bit is always read as zero.

• Bit 6, 3 – WGM21:0: Waveform Generation Mode

These bits control the counting sequence of the counter, the source for the maximum

(TOP) counter value, and what type of waveform generation to be used. Modes of oper-

ation supported by the Timer/Counter unit are: Normal mode, Clear Timer on Compare

match (CTC) mode, and two types of Pulse Width Modulation (PWM) modes. See Table

67 and “Modes of Operation” on page 138.

Note:

1. The CTC2 and PWM2 bit definition names are now obsolete. Use the WGM21:0 def-

initions. However, the functionality and location of these bits are compatible with

previous versions of the timer.

Bit

(0xB0)

FOC2A

WGM20

COM2A1

COM2A0

WGM21

CS22

CS21

CS20

TCCR2A

Read/Write

R/W

Initial Value

Table 67. Waveform Generation Mode Bit Description

(1)

Mode

WGM21

(CTC2)

WGM20

(PWM2)

Timer/Counter Mode

of Operation

TOP

Update of

OCR2A at

TOV2 Flag

Set on

Normal

0xFF

Immediate

MAX

PWM, Phase Correct

0xFF

TOP

BOTTOM

CTC

OCR2A

Immediate

MAX

Fast PWM

0xFF

BOTTOM

MAX

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