ATMEGA649 datasheet(196/375 Pages) ATMEL

196 / 375 page

196

ATmega329/3290/649/6490

2552H–AVR–11/06

When Two-wire mode is selected, the USIPF Flag is set (one) when a stop condition is

detected. The flag is cleared by writing a one to this bit. Note that this is not an Interrupt

Flag. This signal is useful when implementing Two-wire bus master arbitration.

• Bit 4 – USIDC: Data Output Collision

This bit is logical one when bit 7 in the Shift Register differs from the physical pin value.

The flag is only valid when Two-wire mode is used. This signal is useful when imple-

menting Two-wire bus master arbitration.

• Bits 3..0 – USICNT3..0: Counter Value

These bits reflect the current 4-bit counter value. The 4-bit counter value can directly be

read or written by the CPU.

The 4-bit counter increments by one for each clock generated either by the external

clock edge detector, by a Timer/Counter0 Compare Match, or by software using USI-

CLK or USITC strobe bits. The clock source depends of the setting of the USICS1..0

bits. For external clock operation a special feature is added that allows the clock to be

generated by writing to the USITC strobe bit. This feature is enabled by write a one to

the USICLK bit while setting an external clock source (USICS1 = 1).

Note that even when no wire mode is selected (USIWM1..0 = 0) the external clock input

(USCK/SCL) are can still be used by the counter.

ATMEGA649 Datasheet(PDF) 196 Page - ATMEL Corporation