83C795 datasheet(19/136 Pages) SMSC

19 / 136 page

Mnemonic

Pin Number I/O

Description

AE N

PC ADDR E S S E NABLE . Active low. When Addres s E nable is

active the 83C795 responds to any host s trobe (IOR , IOW, ME MR ,

ME MW, SME MR , SME MW).

BALE

PC ADDR E S S LAT CH E NABLE . Us ed to latch valid address es

from the LA bus. Passes LA signals through internal latches while

high and latches them on falling edge.

BS R

115

BIAS R E S IS T OR . A resistor from BS R to VDD s ets the internal

bias levels . Nominal value is 10K

Ω.

CAP

113

PLL F ILT E R CAP. A capacitor (nominal value .01

µF) from CAP to

ground is us ed as part of the filter for the internal phas e lock loop.

CD+

CD-

126

125

AUI COLLIS ION. CD+ /CD- are us ed by the external trans ceiver

to signal a collis ion by sending a 10MHz signal.

EECS

132

E E R OM Chip S elect. An external 9356 serial E E R OM is used to

store up to 2048 bits of configuration data. T hese s ignals (along

with LLE D and R LE D) interface with that chip.

EEDO

137

I/O

EER OM DAT A OUT PUT.

GPOUT

110

GE NE R AL PUR POS E OUT PUT. In some systems, this bit is wired

to a s hutdown control input of the DC/DC is olated power supply

us ed in 10Bas e2 applications . In other systems, this supplies a

control signal for switching power supplies . (T he DC signal’s

polarity on the 83C795 is the oppos ite of the 83C790.)

HOS T CLK

I/O

Pers onal Computer BUS CLOCK.

IO16CS

16 BIT I/O S E LE CT E D. Active low. Indicates to the PC/AT bus that

the I/O response will be 16 bits wide. Only us ed for the I/O pipe.

IOR

I/O

PC I/O R E AD. Active low. R eads an I/O register onto the PC data

bus .

IOR DY

I/O IOR DY. R es pons e to host acces s which can be us ed directly

as ’I/O Channel R eady’ when res ponding to a pers onal computer

bus . It is pulled low (not ready) to lengthen I/O or memory cycles.

When the 83C795 is ready to res pond, the s ignal is driven high

until the host acces s is completed, then becomes tris tated. T his

signal is driven by a tri-s tate buffer capable of s inking 24 mA.

IOW

I/O

PC I/O WR IT E . Active low. Writes an I/O regis ter from the PC data

bus .

IR Q1

108

I/O

PC INT E R R UPT R E QUE S T LINE S . Active high. T ristated when

not active. IR Q2-9 on the PC/AT bus . IR Q1 is the s ame as the

XT XD pin in s ome test modes .

IR Q2

I/O

IR Q3 on PC/AT bus. S ame as XLOOP in some test modes.

IR Q3

106

I/O

IR Q5 on PC/AT bus. S ame as XCR S in some test modes.

IR Q4

107

I/O

IR Q7 on PC/AT bus. S ame as XR XC in some test modes.

IR Q5

I/O

IR Q10 on PC/AT bus . S ame as XR XD in s ome tes t modes .

IR Q6

I/O

IR Q11 on PC/AT bus . S ame as XCOL in s ome tes t modes.

IR Q7

I/O

IR Q15 on PC/AT bus . S ame as XT XC in s ome tes t modes.

TABLE 4-1. 83C795 PIN ASSIGNMENTS

83C795

PIN LIST

83C795 Datasheet(PDF) 19 Page - SMSC Corporation

83C795 Datasheet(HTML) 19 Page - SMSC Corporation

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