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83C795 Datasheet(PDF) 53 Page - SMSC Corporation |
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83C795 Datasheet(HTML) 53 Page - SMSC Corporation |
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53 / 136 page  5.2.48 RENH - Receive Enhancement Register Normal Map R ead/Write Port = 0:19 T he R eceive E nhancement R egis ter contains s everal bits requiredfor thenewreceive features of the 83C795 chip. BIT RENH RESET 7— 0 6— 0 5— 0 4— 0 3— 0 2 REMPTY 0 1 ERFBIT 0 0 WRAPEN 0 Bit 2: REMPTY, Ring Bit Empty When R E MPT Y = 1, this read-only bit indicates that the receive buffer ring has no completely received frames. Bit 1: ERFBIT, Early Receive Fail Bit When E R F BIT = 1 it indicates that an underrun has occurred during the reception of a frame. T he hos t clears this bit after reading the addres s where the failure occurred from the E R FA R egis ters. Bit 0: WRAPEN, Automatic Ring-Wrap Enable When WR APE N = 1 it enables the auto-wrapping feature. For more information on Automatic R ing- Wrap, refer to page 87. 83C795 ETHERNET SYSTEM CONTROLLER REGISTERS 40 |
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