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83C795 Datasheet(PDF) 45 Page - SMSC Corporation |
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83C795 Datasheet(HTML) 45 Page - SMSC Corporation |
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45 / 136 page ![]() Bit 3: GROUP, Receive Multicast Frames When GR OUP = 1, this bit enables reception of all frames that: • have multicast addresses • pass the multicast address hashing filter Bit 2: BROAD, Receive Broadcast Frames When BR OAD = 1, this bit enables reception of all frames having a Broadcas t (all ’1’s ) des tination address . Bit 1: RUNTS, Receive Runts Frames When R UNT S = 1, this bit allows reception of frames having les s than 64 bytes , provided that they otherwis e meet the requirements of the 802.3 protocol. Bit 0: SEP, Save Errored Packets When S E P = 1, it directs the receive unit to s ave packets having CR C or frame alignment errors in the buffers . 5.2.24 RDOWNH - Buffer Room Remaining High Register Linked-List Map R ead/Write Port = 2:19 T his regis ter contains the upper 8 bits of a regis ter pair us ed by the DMA controller as a scratch pad for the buffer room remaining count during the reception proces s . Note Writing to these registers while commu- nication is taking place may cause er- rors in the DMA process. BIT RDOWNH RESET 7 A15 X 6 A14 X 5 A13 X 4 A12 X 3A11 X 2 A10 X 1 A09 X 0 A08 X 5.2.25 RDOWNL - Buffer Room Remaining Low Register Linked-List Map R ead/Write Port = 2:18 T his regis ter contains the lower 8 bits of a regis ter pair us ed by the DMA controller as a scratch pad for the buffer room remaining count during the reception proces s . Note Writing to these registers while commu- nication is taking place may cause er- rors in the DMA process. BIT RDOWNL RESET 7 A07 X 6 A06 X 5 A05 X 4 A04 X 3 A03 X 2 A02 X 1 A01 X 0 A00 X 5.2.26 REND - Receive Buffer End Register Linked-List Map R ead Port = 2:12 Linked-Lis t Map Write Port = 0:12 T his regis ter holds the upper 8 bits of the firs t addres s beyond the end of the receive buffer descriptor table. T he lower 8 bits are as s umed to be zero. T he table lies between the numbers (R BE GIN * 256) and (R E ND * 256 - 1). R efer to page 88 for more details . BIT REND RESET 7 RE15 X 6 RE14 X 5 RE13 X 4 RE12 X 3 RE11 X 2 RE10 X 1 RE9 X 0 RE8 X 83C795 ETHERNET SYSTEM CONTROLLER REGISTERS 32 |
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