83C795 datasheet(51/136 Pages) SMSC

51 / 136 page

5.2.42 TLEVEL - Transmit FIFO Track Register

Normal Map R ead Port = 3:1E

Linked-List Map R ead Port = 3:1E

T his counter tracks the number of empty bytes in

the trans mit FIFO. An empty F IF O has 10h in this

counter. A full FIFO has 00h.

BIT

TLEVEL

RESET

7—

6—

5—

CT04

CT03

CT02

CT01

CT00

5.2.43 TSTARTH - Transmit Start Page High

Normal Map R ead Port = 2:14

Normal Map Write Port = 0:14

T his regis ter is the higher 8 bits of a regis ter pair

that points to the as s embled packet to be

trans mitted. To retain compatibility with 83C690

drivers, the us er s houlds tart all frames on 256-byte

boundaries and not write to T S T ART L.

BIT

TSTARTH

RESET

7A15

6A14

5A13

4A12

3A11

2A10

1A09

0A08

5.2.44 TSTARTL - Transmit Start Page Low

Normal Map R ead/Write Port = 3:15

Linked-List Map R ead/Write Port = 3:15

T his regis ter is thelower 8 bits of aregis ter pair that

points to the as sembled packet to be transmitted.

Toretain compatibility with 83C690 drivers, theus er

s hould s tart all frames on 256-byte boundaries and

only write to the T S T ART H register.

BIT

TSTARTL

RESET

A07

A06

A05

A04

A03

A02

A01

A00

5.2.45 TSTAT - Transmit Status Register

Normal Map R ead Port = 0:14

Linked-List Map R ead Port = 0:14

T he T rans mit S tatus R egis ter reports events that

occur on the media at the end of packet

tr ans mi s s ion. All bits are cleared prior to

trans miss ion of a packet and are s et as needed.

When ALT E GO = 1, the regis ter is cleared only at

the beginning of a transmit chain and is s et after

each packet has completed.

BIT

TSTAT

RESET

7OWC

CDH

UNDER

CRL

ABORT

2TWC

NDT

PTX

Bit 7: OWC, Out of Window Collision

T his bit is set if acollision is detectedmorethan one

s lot time after the start of trans miss ion. T ransmis -

s ion is aborted under thes e conditions .

83C795

ETHERNET SYSTEM CONTROLLER REGISTERS

83C795 Datasheet(PDF) 51 Page - SMSC Corporation

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