LT8640 datasheet(6/35 Pages) AD

6 / 35 page

Data Sheet

LT8638-2

analog.com

Rev.0

6 of 35

PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS

Figure 3. Pin Configuration

Table 3. Pin Descriptions

NAME

DESCRIPTION

Pin 1

PHMODE

Pin determines the phase relationship between the LT8638-2’s internal clock and

CLKOUT. Tie it to GND for 2-phase operation, float the pin for 3-phase operation, or tie

it to INTVCCfor 4-phase operation. See BLOCK DIAGRAM for internal pull-up and pull-

down resistance.

Pin 2

BIAS

The internal regulator draws current from BIAS instead of VIN when BIAS is tied to a

voltage higher than 3.1V. For output voltages of 3.3V to 25V, this pin should be tied to

VOUT. If this pin is tied to a supply other than VOUT, use a 1µF local bypass capacitor on

this pin. If no supply is available, tie to GND. However, especially for high input or high

frequency applications, BIAS should be tied to output or an external supply of 3.3V or

above.

Pin 3

INTVCC

Internal 3.4V Regulator Bypass Pin. The internal power drivers and control circuits are

powered from this voltage. Do not load the INTVCC pin with external circuitry. INTVCC

current is supplied from BIAS if BIAS > 3.1V, otherwise current is drawn from VIN.

Voltage on INTVCC varies between 2.8V and 3.4V when BIAS is between 3.0V and 3.6V.

Place a low ESR ceramic capacitor of at least 1µF from this pin to ground close to the

IC.

LT8638-2

TOP VIEW

(Not to Scale)

PHMODE

BIAS

INTVCC

BST

EN/UV

GND

VIN

GND

LQFN PACKAGE

28-LEAD (5mm × 4mm × 0.94mm)

JEDEC BOARD:

θJA = 30°C/W, θJC(TOP) = 14.7°C/W, θJC(PAD) = 2.7°C/W (NOTE 4)

DEMO BOARD:

θJA = 19°C/W, ΨJT = 0.1°C/W

EXPOSED PADS (PINS 29 TO 32) ARE GND, MUST BE SOLDERED TO PCB FOR

OPTIMAL THERMAL PERFORMANCE.

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