C8051F340 datasheet(45/288 Pages) SILABS

45 / 288 page

Rev. 1.0

C8051F340/1/2/3/4/5/6/7

5. 10-Bit ADC (ADC0)

The ADC0 subsystem for the C8051F340/1/2/3/4/5/6/7 consists of two analog multiplexers (referred to col-

lectively as AMUX0), and a 200 ksps, 10-bit successive-approximation-register ADC with integrated

track-and-hold and programmable window detector. The AMUX0, data conversion modes, and window

detector are all configured under software control via the Special Function Registers shown in Figure 5.1.

ADC0 operates in both Single-ended and Differential modes, and may be configured to measure voltages

at port pins, the Temperature Sensor output, or VDD with respect to a port pin, VREF, or GND. The connec-

tion options for AMUX0 are detailed in SFR Definition 5.1 and SFR Definition 5.2. The ADC0 subsystem is

enabled only when the AD0EN bit in the ADC0 Control register (ADC0CN) is set to logic 1. The ADC0 sub-

system is in low power shutdown when this bit is logic 0.

ADC0CF

10-Bit

SAR

ADC

ADC0CN

Timer 0 Overflow

Timer 2 Overflow

Timer 1 Overflow

Start

Conversion

000

AD0BUSY (W)

VDD

ADC0LTH

AD0WINT

001

010

011

100

CNVSTR Input

Window

Compare

Logic

GND

101

Timer 3 Overflow

ADC0LTL

ADC0GTH ADC0GTL

AMX0P

AMX0N

AIN+

AIN-

VREF

Positive

Input

(AIN+)

AMUX

VDD

Negative

Input

(AIN-)

AMUX

Temp

Sensor

Port I/O

Pins*

Port I/O

Pins*

* 21 Selections on 32-pin package

20 Selections on 48-pin package

Figure 5.1. ADC0 Functional Block Diagram

C8051F340 Datasheet(PDF) 45 Page - Silicon Laboratories

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