C8051F340 datasheet(10/288 Pages) SILABS

10 / 288 page

C8051F340/1/2/3/4/5/6/7

Rev. 1.0

11. Reset Sources

Figure 11.1. Reset Sources.................................................................................... 105

Figure 11.2. Power-On and VDD Monitor Reset Timing ........................................ 106

12. Flash Memory

Figure 12.1. Flash Program Memory Map and Security Byte................................. 116

13. External Data Memory Interface and On-Chip XRAM

Figure 13.1. USB FIFO Space and XRAM Memory Map with USBFAE set to ‘1’ .. 122

Figure 13.2. Multiplexed Configuration Example.................................................... 126

Figure 13.3. Non-multiplexed Configuration Example ............................................ 127

Figure 13.4. EMIF Operating Modes ...................................................................... 127

Figure 13.5. Non-multiplexed 16-bit MOVX Timing ................................................ 131

Figure 13.6. Non-multiplexed 8-bit MOVX without Bank Select Timing ................. 132

Figure 13.7. Non-multiplexed 8-bit MOVX with Bank Select Timing ...................... 133

Figure 13.8. Multiplexed 16-bit MOVX Timing........................................................ 134

Figure 13.9. Multiplexed 8-bit MOVX without Bank Select Timing ......................... 135

Figure 13.10. Multiplexed 8-bit MOVX with Bank Select Timing ............................ 136

14. Oscillators

Figure 14.1. Oscillator Diagram.............................................................................. 139

15. Port Input/Output

Figure 15.1. Port I/O Functional Block Diagram (Port 0 through Port 3) ................ 151

Figure 15.2. Port I/O Cell Block Diagram ............................................................... 152

Figure 15.3. Crossbar Priority Decoder with No Pins Skipped ............................... 153

Figure 15.4. Crossbar Priority Decoder with Crystal Pins Skipped ........................ 154

16. Universal Serial Bus Controller (USB0)

Figure 16.1. USB0 Block Diagram.......................................................................... 167

Figure 16.2. USB0 Register Access Scheme......................................................... 170

Figure 16.3. USB FIFO Allocation .......................................................................... 175

17. SMBus

Figure 17.1. SMBus Block Diagram ....................................................................... 197

Figure 17.2. Typical SMBus Configuration ............................................................. 198

Figure 17.3. SMBus Transaction ............................................................................ 199

Figure 17.4. Typical SMBus SCL Generation......................................................... 203

Figure 17.5. Typical Master Transmitter Sequence................................................ 209

Figure 17.6. Typical Master Receiver Sequence.................................................... 210

Figure 17.7. Typical Slave Receiver Sequence...................................................... 211

Figure 17.8. Typical Slave Transmitter Sequence.................................................. 212

18. UART0

Figure 18.1. UART0 Block Diagram ....................................................................... 215

Figure 18.2. UART0 Baud Rate Logic .................................................................... 216

Figure 18.3. UART Interconnect Diagram .............................................................. 217

Figure 18.4. 8-Bit UART Timing Diagram............................................................... 217

Figure 18.5. 9-Bit UART Timing Diagram............................................................... 218

Figure 18.6. UART Multi-Processor Mode Interconnect Diagram .......................... 219

19. UART1 (C8051F340/1/4/5 Only)

Figure 19.1. UART1 Block Diagram ....................................................................... 223

C8051F340 Datasheet(PDF) 10 Page - Silicon Laboratories

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