C8051F340 datasheet(6/288 Pages) SILABS

6 / 288 page

C8051F340/1/2/3/4/5/6/7

Rev. 1.0

17.2.SMBus Configuration...................................................................................... 198

17.3.SMBus Operation ........................................................................................... 198

17.3.1.Arbitration............................................................................................... 199

17.3.2.Clock Low Extension.............................................................................. 200

17.3.3.SCL Low Timeout................................................................................... 200

17.3.4.SCL High (SMBus Free) Timeout .......................................................... 200

17.4.Using the SMBus............................................................................................ 200

17.4.1.SMBus Configuration Register............................................................... 202

17.4.2.SMB0CN Control Register ..................................................................... 205

17.4.3.Data Register ......................................................................................... 208

17.5.SMBus Transfer Modes.................................................................................. 208

17.5.1.Master Transmitter Mode ....................................................................... 208

17.5.2.Master Receiver Mode ........................................................................... 210

17.5.3.Slave Receiver Mode ............................................................................. 211

17.5.4.Slave Transmitter Mode ......................................................................... 212

17.6.SMBus Status Decoding................................................................................. 212

18. UART0.................................................................................................................... 215

18.1.Enhanced Baud Rate Generation................................................................... 216

18.2.Operational Modes ......................................................................................... 216

18.2.1.8-Bit UART ............................................................................................. 217

18.2.2.9-Bit UART ............................................................................................. 218

18.3.Multiprocessor Communications .................................................................... 218

19. UART1 (C8051F340/1/4/5 Only) ........................................................................... 223

19.1.Baud Rate Generator ..................................................................................... 224

19.2.Data Format.................................................................................................... 225

19.3.Configuration and Operation .......................................................................... 226

19.3.1.Data Transmission ................................................................................. 226

19.3.2.Data Reception ...................................................................................... 226

19.3.3.Multiprocessor Communications ............................................................ 227

20. Enhanced Serial Peripheral Interface (SPI0)...................................................... 233

20.1.Signal Descriptions......................................................................................... 234

20.1.1.Master Out, Slave In (MOSI).................................................................. 234

20.1.2.Master In, Slave Out (MISO).................................................................. 234

20.1.3.Serial Clock (SCK) ................................................................................. 234

20.1.4.Slave Select (NSS) ................................................................................ 234

20.2.SPI0 Master Mode Operation ......................................................................... 235

20.3.SPI0 Slave Mode Operation ........................................................................... 237

20.4.SPI0 Interrupt Sources ................................................................................... 237

20.5.Serial Clock Timing......................................................................................... 238

20.6.SPI Special Function Registers ...................................................................... 240

21. Timers.................................................................................................................... 247

21.1.Timer 0 and Timer 1 ....................................................................................... 247

21.1.1.Mode 0: 13-bit Counter/Timer ................................................................ 247

21.1.2.Mode 1: 16-bit Counter/Timer ................................................................ 248

21.1.3.Mode 2: 8-bit Counter/Timer with Auto-Reload...................................... 249

C8051F340 Datasheet(PDF) 6 Page - Silicon Laboratories

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