C8051F340 datasheet(49/288 Pages) SILABS

49 / 288 page

Rev. 1.0

C8051F340/1/2/3/4/5/6/7

5.3.

Modes of Operation

ADC0 has a maximum conversion speed of 200 ksps. The ADC0 conversion clock is a divided version of

the system clock, determined by the AD0SC bits in the ADC0CF register (system clock divided by

(AD0SC + 1) for 0

≤ AD0SC ≤ 31).

5.3.1. Starting a Conversion

A conversion can be initiated in one of five ways, depending on the programmed states of the ADC0 Start

of Conversion Mode bits (AD0CM2–0) in register ADC0CN. Conversions may be initiated by one of the fol-

lowing:

1. Writing a ‘1’ to the AD0BUSY bit of register ADC0CN

2. A Timer 0 overflow (i.e., timed continuous conversions)

3. A Timer 2 overflow

4. A Timer 1 overflow

5. A rising edge on the CNVSTR input signal

6. A Timer 3 overflow

Writing a ‘1’ to AD0BUSY provides software control of ADC0 whereby conversions are performed

"on-demand". During conversion, the AD0BUSY bit is set to logic 1 and reset to logic 0 when the conver-

sion is complete. The falling edge of AD0BUSY triggers an interrupt (when enabled) and sets the ADC0

interrupt flag (AD0INT). Note: When polling for ADC conversion completions, the ADC0 interrupt flag

(AD0INT) should be used. Converted data is available in the ADC0 data registers, ADC0H:ADC0L, when

bit AD0INT is logic 1. Note that when Timer 2 or Timer 3 overflows are used as the conversion source, Low

Byte overflows are used if Timer 2/3 is in 8-bit mode; High byte overflows are used if Timer 2/3 is in 16-bit

mode. See

Section “21. Timers” on page 247 for timer configuration.

Important Note About Using CNVSTR: The CNVSTR input pin also functions as a Port pin. When the

CNVSTR input is used as the ADC0 conversion source, the associated Port pin should be skipped by the

Digital Crossbar. To configure the Crossbar to skip a pin, set the corresponding bit in the PnSKIP register

to ‘1’. See

Section “15. Port Input/Output” on page 151 for details on Port I/O configuration.

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