ISO1228DFBR datasheet(32/44 Pages) TI1

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10 Layout

10.1 Layout Guidelines

The board layout for ISO1228 can be completed in two layers. On the field side, place RTHR, CIN, RPAR,

RILIM, CFIL, RSURGE, and CSURGE on the top layer. Use the bottom layer as the field ground (FGND) plane. TI

recommends using RPAR and CIN in 0603 footprints for a compact layout, although larger sizes (0805) can also

be used. The CIN capacitor is a 50V capacitor and is available in the 0603 footprint. Keep CIN as close to the

ISO1228 device as possible. TI recommends using RTHR, RSURGE, RILIM in MELF 0204 footprint surge-proof

resistors and 0805 footprint 50V capacitors for CSURGE and CFIL. The placement of the RTHR resistor is flexible,

although the resistor pin connected to external high voltage should not be placed within 4mm of the ISO1228

device pins or the CIN and RPAR pins to avoid flashover during EMC tests. The placement of LEDs is flexible to

display the channel status on the field side.

Only a decoupling capacitor is required on side 1. Place this capacitor on the top-layer, with the bottom layer for

GND1.

Layout Example shows the example layout.

10.2 Layout Example

High Voltage

Input

MCU

RTHR

INP1

LED

IN1

LED1

IN8

LED8

AVSS

AVCC

LED

RTHR

INP8

V24V

FGND

COMM_SEL

VCC1

GND1

nCS

SDO

VCC

FGND

Plane

GND1

Plane

SDI

SCLK

2 mm Maximum from

VCC1

Follow Similar Placement for

other channels

Trace length of SPI Lines needs

to be matched

RSURGE

RILIM

CFIL

CSURGE

Figure 10-1. Layout Example With ISO1228

ISO1228

SLLSFN5A – JUNE 2023 – REVISED FEBRUARY 2024

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