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ISO1228DFBR Datasheet(PDF) 12 Page - Texas Instruments |
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ISO1228DFBR Datasheet(HTML) 12 Page - Texas Instruments |
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12 / 44 page  (Over recommended operating conditions unless otherwise noted). PARAMETER TEST CONDITIONS MIN TYP MAX UNIT VOLTAGE TRANSITION THRESHOLD ON FIELD SIDE VIL Low level threshold voltage at module input (including RTHR) for output low. Sink Type. RILIM = 1 kΩ or 0 Ω,RTHR = 0 Ω 4.7 V RILIM = 1 kΩ, RTHR = 1 kΩ 7.7 VIL Low level threshold voltage at module input (including RTHR) for output low. Sink Type. RILIM = 0 Ω, RTHR = 1 kΩ 6.7 V VIH High level threshold voltage at module input (including RTHR) for output high. Sink Type. RILIM = 1 kΩ or 0 Ω, RTHR = 0 Ω 6.4 V RILIM = 1 kΩ, RTHR = 1 kΩ 11.1 RILIM = 0 Ω, RTHR = 1 kΩ 9.7 VHYS Threshold voltage hysteresis at module input. Sink Type. RILIM = 1 kΩ, RTHR = 0 Ω 0.85 1 V RILIM = 1 kΩ, RTHR = 1 kΩ 0.8 1 RILIM = 0 Ω, RTHR = 1 kΩ 0.7 1 AVCC-VIL Low level threshold voltage at module input (including RTHR) for output low. Source Type. RILIM = 0 Ω, RTHR = 1.35k Ω 7.4 V RILIM = 1 kΩ, RTHR = 2 kΩ 10.7 V AVCC-VIH High level threshold voltage at module input (including RTHR) for output high. Source Type. RILIM = 0 Ω, RTHR = 1.35k Ω 10.9 V RILIM = 1 kΩ, RTHR = 2 kΩ 14.8 V VHYS Threshold voltage hysteresis at module input. Source Type. RILIM = 1 kΩ, RTHR = 2 kΩ 0.5 V RILIM = 0 Ω, RTHR = 1.35k Ω 0.75 1 V OVER-TEMPERATURE AND THERMAL SHUTDOWN OTI Over-temperature indication without shutdown (No blocks are shut down) 130 142 150 °C TSD+ Thermal shutdown turn-on temperature (Field Inputs are tri-stated) 160 180 190 °C TSD- Thermal shutdown turn-off temperature 155 170 180 °C TSDHYS Thermal shutdown hysteresis 5 °C (1) RIWB is the wire break resistance calculated from the equation, RIWB = (VINX -2V) /IWB - RTHR 5.10 Switching Characteristics—AC Specification (Over recommended operating conditions unless otherwise noted). PARAMETER TEST CONDITIONS MIN TYP MAX UNIT POWER-UP TIMING TPWRUP Time taken for the device to power up, and start communication after VCC1 and AVCC are above their UVLO levels. VCC1 and AVCC are ramped up together. 140 200 µs TFILTAVCC Internal de-glitch filter on AVCC AVCC supply dip to corresponding UVLO- thresholds with 10 ns rise/fall times. 3 5 7 µs TFILTVCC1 Internal de-glitch filter on VCC1 - recovery time VCC1 supply dip to UVLO- thresholds with 10 ns rise/fall times upto 9us. Time needed by device to be functional again 1 4 7 µs PROPAGATION DELAY AND CMTI tr, tf Output signal rise and fall time, OUTx pins CLOAD = 15 pF, 24-VP-P clock signal on IN pin with 10-ns rise and fall time, RTHR = 0 Ω. Parallel output mode. F1=low, F0=low; Filter Register setting: 0xxx 3 ns ISO1228 SLLSFN5A – JUNE 2023 – REVISED FEBRUARY 2024 www.ti.com 12 Submit Document Feedback Copyright © 2024 Texas Instruments Incorporated Product Folder Links: ISO1228 |
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