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TMD2712 Datasheet(PDF) 19 Page - OSRAM GmbH |
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TMD2712 Datasheet(HTML) 19 Page - OSRAM GmbH |
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19 / 54 page ![]() Page 18 Datasheet, Public Document Feedback [v4-00] 2023-Jan-02 TMD2712 − Register Description AWTIME Register (Address 0x83) Figure 20: AWTIME Register The wait timer is implemented using a down counter. Wait time = Increment x 2.78ms. If AWLONG is enabled then Wait time = Increment x 2.78ms x 12. AILTL Register (Address 0x84) Figure 21: AILTL Register AILTH Register (Address 0x85) Figure 22: AILTH Register Addr: 0x83 AWTIME Bit Bit Name Default Access Bit Description 7:0 AWTIME 0x00 RW Value that specifies the wait time in 2.78ms increments. Value Increments Wait Time 0x00 1 2.78ms (33.4ms) 0x01 2 5.56ms (66.7ms) 0x11 18 50.0ms (600ms) 0x23 36 100ms (1.20s) 0x3F 64 178ms (2.14s) 0xFF 256 712ms (8.54s) Addr: 0x84 AILTL Bit Bit Name Default Access Bit Description 7:0 AILTL 0x00 RW This register sets the low byte of the LOW ALS threshold. Addr: 0x85 AILTH Bit Bit Name Default Access Bit Description 7:0 AILTH 0x00 RW This register sets the high byte of the LOW ALS threshold. |
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