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TMD2712 Datasheet(PDF) 24 Page - OSRAM GmbH |
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TMD2712 Datasheet(HTML) 24 Page - OSRAM GmbH |
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24 / 54 page  Datasheet, Public Page 23 [v4-00] 2023-Jan-02 Document Feedback TMD2712 − Register Description The frequency of consecutive ALS (CH0) channel results outside of threshold limits are counted; this count value is compared against the APERS value. If the counter is equal to the APERS setting an interrupt is asserted. Any time an ALS (CH0) channel result is inside the threshold values the counter is cleared. CFG0 Register (Address 0x8D) Figure 30: CFG0 Register Addr: 0x8D CFG0 Bit Bit Name Default Access Bit Description 7:4 Reserved 0101 RW Reserved. Must be set to default value. 3 POFFSET_ SCALE 1RW If set to 0, the range of POFFSET and LSB step size is increased by a factor of ~2x 2PWLONG 0 RW When PWLONG (PROX Wait Long) is asserted the wait period as set by PWTIME is increased by a factor of 12. 1AWLONG 0 RW When AWLONG (ALS Wait Long) is asserted the wait period as set by AWTIME is increased by a factor of 12. 0 Reserved 0 RW Reserved. Must be set to default value. |
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