AD7367 datasheet(7/28 Pages) AD

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AD7366/AD7367

Rev. 0 | Page 7 of 28

TIMING SPECIFICATIONS

AVCC = DVCC = 4.75 V to 5.25 V, VDD = 11.5 V to 16.5 V, VSS = −16.5 V to −11.5 V, VDRIVE = 2.7 V to 5.25 V, TA = TMIN to TMAX, unless

otherwise noted.1

Table 4.

Limit at TMIN, TMAX

Parameter

2.7 V ≤ VDRIVE < 4.75 V

4.75 V ≤ VDRIVE ≤ 5.25 V

Unit

Test Conditions/Comments

tCONVERT

Conversion time, internal clock. CONVST falling edge to

BUSY falling edge

680

ns max

For the AD7367

610

ns max

For the AD7366

fSCLK

kHz min

Frequency of serial read clock

MHz max

tQUIET

ns min

Minimum quiet time required between the end of serial

read and the start of the next conversion

ns min

Minimum CONVST low pulse

ns min

CONVST falling edge to BUSY rising edge

ns min

BUSY falling edge to MSB valid once CS is low for t4 prior to

BUSY going low

ns max

Delay from CS falling edge until Pin 1 (DOUTA) and Pin 23

(DOUTB) are three-state disabled

t52

ns max

Data access time after SCLK falling edge

ns min

SCLK to data valid hold time

0.3 × tSCLK

ns min

SCLK low pulse width

0.3 × tSCLK

ns min

SCLK high pulse width

ns max

CS rising edge to DOUTA, DOUTB, high impedance

tPOWER-UP

μs

Power up time from shutdown mode; time required

between CONVST rising edge and CONVST falling edge

1 Sample tested during initial release to ensure compliance. All input signals are specified with tR = tF = 5 ns (10% to 90% of VDRIVE) and timed from a voltage level of 1.6 V.

All timing specifications given are with a 25 pF load capacitance. With a load capacitance greater than this value, a digital buffer or latch must be used. See the

Terminology section and Figure 25.

2 The time required for the output to cross is 0.4 V or 2.4 V.

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