AD7367 datasheet(17/28 Pages) AD

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AD7366/AD7367

Rev. 0 | Page 17 of 28

VDD

VIN0

VSS

Figure 18. Equivalent Analog Input Structure

The AD7366/AD7367 can handle true bipolar input voltages.

The analog input can be set to one of three ranges: ±10 V, ±5 V,

or 0 V to 10 V. The logic levels on Pin RANGE0 and Pin RANGE1

determine which input range is selected as outlined in Table 8.

These range bits should not be changed during the acquisition

time prior to a conversion, but can change at any other time.

Table 8. Analog Input Range Selection

RANGE1

RANGE0

Range Selected

±10 V

±5 V

0 V to 10 V

Do not program

The AD7366/AD7367 require VDD and VSS dual supplies for the

high voltage analog input structures. These supplies must be

equal to or greater than ±11.5 V. See Table 7 for the require-

ments on these supplies. The AD7366/AD7367 require a low

voltage 4.75 V to 5.25 V AVCC supply to power the ADC core,

a 4.75 V to 5.25 V DVCC supply for digital power, and a 2.7 V

to 5.25 V VDRIVE supply for interface power.

Channel selection is made via the ADDR pin as shown in

Table 9. The logic level on the ADDR pin is latched on the

rising edge of the BUSY signal for the next conversion, not

the one in progress. When power is first supplied to the

AD7366/AD7367 the default channel selection is VA1 and VB1.

Table 9. Channel Selection

ADDR

Channels Selected

VA1, VB1

VA2, VB2

TRANSFER FUNCTION

The output coding of the AD7366/AD7367 is twos complement.

The designed code transitions occur at successive integer LSB

values (that is, 1 LSB, 2 LSB, and so on). The LSB size is dependent

on the analog input range selected. The ideal transfer charac-

teristic is shown in Figure 19.

Table 10. LSB Sizes for Each Analog Input Range

AD7366

AD7367

Input

Range

Full-Scale

Range

LSB Size

(mV)

Full-Scale

Range

LSB Size

(mV)

±10 V

20 V/4096

4.88

20 V/16384

1.22

±5 V

10 V/4096

2.44

10 V/16384

0.61

0 V to 10 V

10 V/4096

2.44

10 V/16384

0.61

+FSR/2 – 1LSB

ANALOG INPUT

011...111

011...110

000...001

000...000

111...111

100...010

100...001

100...000

–FSR/2 + 1LSB

Figure 19. Transfer Characteristic

Track-and-Hold

The track-and-hold on the analog input of the AD7366/AD7367

allows the ADC to accurately convert an input sine wave of full-

scale amplitude to 12-/14-bit accuracy. The input bandwidth of

the track-and-hold is greater than the Nyquist rate of the ADC.

The AD7366/AD7367 can handle frequencies up to 35 MHz.

The track-and-hold enters its tracking mode once the BUSY

signal goes low after the CS falling edge. The time required to

acquire an input signal depends on how quickly the sampling

capacitor is charged. With zero source impedance, 140 ns is suffi-

cient to acquire the signal to the 12-bit for the AD7366 and the

14-bit level for the AD7367. The acquisition time for the ±10 V,

±5 V, and 0 V to +10 V ranges to settle to within ±½ LSB is

typically 140 ns. The ADC goes back into hold mode on the

falling edge of CNVST.

The acquisition time required is calculated using the following

formula:

tACQ = 10 × ((RSOURCE + R) C)

where:

C is the sampling capacitance.

R is the resistance seen by the track-and-hold amplifier looking

at the input.

RSOURCE should include any extra source impedance on the

analog input.

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