AD7367 datasheet(22/28 Pages) AD

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AD7366/AD7367

Rev. 0 | Page 22 of 28

SERIAL INTERFACE

Figure 25 and Figure 26 show the detailed timing diagram

for serial interfacing to the AD7366 and the AD7367. On the

falling edge of CNVST the AD7366/AD7367 simultaneously

converts the selected channels. These conversions are performed

using the on-chip oscillator. After the falling edge of CNVST

the BUSY signal goes high, indicating the conversion has started.

It returns low once the conversion has been completed. The data

can now be read from the

DOUT pins.

CS and SCLK signals are required to transfer data from the

AD7366/AD7367. The AD7366/AD7367 have two output pins

corresponding to each ADC. Data can be read from the AD7366/

AD7367 using both DOUTA and DOUTB. Alternatively, a single

output pin of the user’s choice can be used. The SCLK input

signal provides the clock source for the serial interface. The CS

goes low to access data from the AD7366/AD7367. The falling

edge of CS takes the bus out of three-state and clocks out the

MSB of the conversion result. The data stream consists of

12 bits of data for the AD7366 and 14 bits of data for the

AD7367, MSB first. The first bit of the conversion result is

valid on the first SCLK falling edge after the CS falling edge.

The subsequent 11-/13-bits of data for the AD7366/AD7367

respectively are clocked out on the falling edge of the SCLK

signal. A minimum of 12 clock pulses must be provided to

AD7366 to access each conversion result, while a minimum

of 14 clock pulses must be provided to AD7367 to access the

conversion result. Figure 25 shows how a 12 SCLK read is used

to access the conversion results while Figure 26 illustrates the

case for the AD7367 with a 14 SCLK read.

On the rising edge of CS, the conversion is terminated and

DOUTA and DOUTB go back into three-state. If CS is not brought

high, but is instead held low for a further 12 SCLK cycles for the

AD7366 or 14 SCLK cycles for the AD7367, on either DOUTA or

DOUTB, the data from the other ADC follows on the DOUT pin.

This is illustrated in Figure 27 and Figure 28 where the case for

DOUTA is shown. In this case, the DOUT line in use goes back into

three-state on the rising edge of CS.

If the falling edge of SCLK coincides with the falling edge of

CS, then the falling edge of SCLK is not acknowledged by the

AD7366/AD7367, and the next falling edge of the SCLK is the

first registered after the falling edges of the CS.

The CS pin can be brought low before the BUSY signal goes

low indicating the end of a conversion. Once CS is at a logic low

state the data bus is brought out of three-state. This feature can

be utilized to ensure that the MSB is valid on the falling edge of

BUSY by bring CS low a minimum of t4 nanoseconds before the

BUSY signal goes low. The dotted CS

line in Figure 22 and

Figure 23 illustrates this.

Alternatively, the CS pin can be tied to a low logic state continu-

ously. Now the DOUT pins never enter three-state and the data

bus is continuously active. Under these conditions, the MSB of

the conversion result for the AD7366/AD7367 is available on

the falling edge of the BUSY signal. The next most significant

bit is available on the first SCLK falling edge after the BUSY

signal has gone low. This mode of operation enables the user to

read the MSB as soon as it is made available by the converter.

DOUTA

DOUTB THREE-

STATE

THREE-STATE

SCLK

512

DB10

DB11

DB9

DB8

DB2

DB1

DB0

Figure 25. Serial Interface Timing Diagram for the AD7366

DOUTA

DOUTB THREE-

STATE

THREE-STATE

SCLK

514

DB12

DB13

DB11

DB10

DB2

DB1

DB0

Figure 26. Serial Interface Timing Diagram for the AD7367

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