56853 datasheet(30/60 Pages) FREESCALE

30 / 60 page

56853 Technical Data, Rev. 6

Freescale Semiconductor

Figure 4-8 Connecting a Low Speed External Clock Signal using XTAL

Figure 4-9 External Clock Timing

Table 4-5 External Clock Operation Timing Requirements4

Operating Conditions: VSS = VSSIO = VSSA = 0 V, VDD = 1.62-1.98V, VDDIO = VDDA = 3.0–3.6V, TA = –40° to +120°C, CL ≤ 50pF, fop = 120MHz

Characteristic

Symbol

Min

Typ

Max

Unit

Frequency of operation (external clock driver)1

See Figure 4-7 for details on using the recommended connection of an external clock driver.

fosc

—

240

MHz

Clock Pulse Width4

tPW

6.25

—

External clock input rise time2, 4

External clock input rise time is measured from 10% to 90%.

trise

—

TBD

External clock input fall time3, 4

External clock input fall time is measured from 90% to 10%.

Parameters listed are guaranteed by design.

tfall

—

TBD

DSP56853

XTAL

EXTAL

External

Clock

(2-4MHz)

VDDA/2

External

Clock

VIH

VIL

Note: The midpoint is VIL + (VIH – VIL)/2.

90%

50%

10%

90%

50%

10% t

tPW

tfall

trise

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