56853 datasheet(32/60 Pages) FREESCALE

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56853 Technical Data, Rev. 6

Freescale Semiconductor

Figure 4-10 External Memory Interface Timing

Table 4-7 External Memory Interface Timing

Operating Conditions: VSS = VSSIO = VSSA = 0 V, VDD = 1.62-1.98 V, VDDIO = VDDA = 3.0–3.6V, TA = –40× to +120×C, CL £ 50pF, P = 8.333ns

Characteristic

Symbol

Wait States

Configuration

Wait States

Controls

Unit

Address Valid to WR Asserted

tAWR

WWS=0

-0.79

0.50

WWSS

WWS>0

-1.98

0.69

WR Width Asserted to WR

Deasserted

tWR

WWS=0

-0.86

0.19

WWS

WWS>0

-0.01

0.00

Data Out Valid to WR Asserted

tDWR

WWS=0

-1.52

0.00

WWSS

WWS=0

- 5.69

0.25

WWS>0

-2.10

0.19

WWS>0

-4.66

0.50

Valid Data Out Hold Time after WR

Deasserted

tDOH

-1.47

0.25

WWSH

Valid Data Out Set Up Time to WR

Deasserted

tDOS

-2.36

0.19

WWS,WWSS

-4.67

0.50

Valid Address after WR

Deasserted

tWAC

-1.60

0.25

WWSH

tDRD

tRDD

tAD

tDOH

tDOS

tDWR

tRDWR

tWAC

tWRRD

tWR

tAWR

tWRWR

tARDD

tRDA

tRDRD

tRD

tARDA

Data Out

Data In

A0-Axx,CS

D0-D15

Note: During read-modify-write instructions and internal instructions, the address lines do not change state.

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