56853 datasheet(55/60 Pages) FREESCALE

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Electrical Design Considerations

56853 Technical Data, Rev. 6

Freescale Semiconductor

thermal resistance to estimate junction temperature from a thermocouple reading on the case of the package will

estimate a junction temperature slightly hotter than actual. Hence, the new thermal metric, Thermal Characterization

Parameter, or

ΨJT, has been defined to be (TJ – TT)/PD. This value gives a better estimate of the junction temperature

in natural convection when using the surface temperature of the package. Remember that surface temperature

readings of packages are subject to significant errors caused by inadequate attachment of the sensor to the surface

and to errors caused by heat loss to the sensor. The recommended technique is to attach a 40-gauge thermocouple

wire and bead to the top center of the package with thermally conductive epoxy.

6.2 Electrical Design Considerations

Use the following list of considerations to assure correct operation:

•

Provide a low-impedance path from the board power supply to each VDD pin on the device, and from the

board ground to each VSS (GND) pin.

•

The minimum bypass requirement is to place six 0.01–0.1

μF capacitors positioned as close as possible to

the package supply pins. The recommended bypass configuration is to place one bypass capacitor on each

of the ten VDD/VSS pairs, including VDDA/VSSA.

•

Ensure that capacitor leads and associated printed circuit traces that connect to the chip VDD and VSS (GND)

pins are less than 0.5 inch per capacitor lead.

•

Use at least a four-layer Printed Circuit Board (PCB) with two inner layers for VDD and GND.

•

Bypass the VDD and GND layers of the PCB with approximately 100 μF, preferably with a high-grade

capacitor such as a tantalum capacitor.

•

Because the device’s output signals have fast rise and fall times, PCB trace lengths should be minimal.

•

Consider all device loads as well as parasitic capacitance due to PCB traces when calculating capacitance.

This is especially critical in systems with higher capacitive loads that could create higher transient currents

in the VDD and GND circuits.

•

All inputs must be terminated (i.e., not allowed to float) using CMOS levels.

•

Take special care to minimize noise levels on the VDDA and VSSA pins.

•

When using Wired-OR mode on the SPI or the IRQx pins, the user must provide an external pull-up device.

CAUTION

This device contains protective circuitry to guard against

damage due to high static voltage or electrical fields.

However, normal precautions are advised to avoid

application of any voltages higher than maximum rated

voltages to this high-impedance circuit. Reliability of

operation is enhanced if unused inputs are tied to an

appropriate voltage level.

56853 Datasheet(PDF) 55 Page - Freescale Semiconductor, Inc

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