56853 datasheet(43/60 Pages) FREESCALE

43 / 60 page

Quad Timer Timing

56853 Technical Data, Rev. 6

Freescale Semiconductor

4.10 Quad Timer Timing

Figure 4-27 Timer Timing

4.11 Enhanced Synchronous Serial Interface (ESSI) Timing

Table 4-11 Quad Timer Timing1, 2

Operating Conditions: VSS = VSSIO = VSSA = 0 V, VDD = 1.62-1.98V, VDDIO = VDDA = 3.0–3.6V, TA = –40° to +120°C, CL ≤ 50pF, fop = 120MHz

In the formulas listed, T = clock cycle. For fop = 120MHz operation and fipb = 60MHz, T = 8.33ns.

Parameters listed are guaranteed by design.

Characteristic

Symbol

Min

Max

Unit

Timer input period

2T + 3

—

Timer input high/low period

PINHL

1T + 3

—

Timer output period

POUT

2T - 3

—

Timer output high/low period

POUTHL

1T - 3

—

Table 4-12 ESSI Master Mode1 Switching Characteristics

Operating Conditions: VSS = VSSIO = VSSA = 0 V, VDD = 1.62-1.98V, VDDIO = VDDA = 3.0–3.6V, TA = –40° to +120°C, CL ≤ 50pF, fop = 120MHz

Parameter

Symbol

Min

Typ

Max

Units

SCK frequency

—

152

MHz

SCK period3

tSCKW

66.7

—

SCK high time

tSCKH

33.44

—

SCK low time

tSCKL

33.44

—

Output clock rise/fall time

—

Delay from SCK high to SC2 (bl) high - Master5

tTFSBHM

-1.0

—

1.0

Timer Inputs

Timer Outputs

PINHL

POUTHL

POUT

56853 Datasheet(PDF) 43 Page - Freescale Semiconductor, Inc

56853 Datasheet(HTML) 43 Page - Freescale Semiconductor, Inc

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60

Datasheet Download

Link URL