56F8366 datasheet(135/184 Pages) FREESCALE

135 / 184 page

Flash Access Blocking Mechanisms

56F8366 Technical Data, Rev. 6

Freescale Semiconductor

135

Preliminary

7.2.2

Disabling EOnCE Access

On-chip Flash can be read by issuing commands across the EOnCE port, which is the debug interface for

the 56800E core. The TRST, TCLK, TMS, TDO, and TDI pins comprise a JTAG interface onto which the

EOnCE port functionality is mapped. When the device boots, the chip-level JTAG TAP (Test Access Port)

is active and provides the chip’s boundary scan capability and access to the ID register.

Proper implementation of Flash security requires that no access to the EOnCE port is provided when

security is enabled. The 56800E core has an input which disables reading of internal memory via the

JTAG/EOnCE. The FM sets this input at reset to a value determined by the contents of the FM security

bytes.

7.2.3

Flash Lockout Recovery

If a user inadvertently enables Flash security on the device, a built-in lockout recovery mechanism can be

used to reenable access to the device. This mechanism completely reases all on-chip Flash, thus disabling

Flash security. Access to this recovery mechanism is built into CodeWarrior via an instruction in memory

configuration (.cfg) files. Add, or uncomment the following configuration command:

unlock_flash_on_connect 1

For more information, please see CodeWarrior MC56F83xx/DSP5685x Family Targeting Manual.

The LOCKOUT_RECOVERY instruction has an associated 7-bit Data Register (DR) that is used to

control the clock divider circuit within the FM module. This divider, FM_CLKDIV[6:0], is used to control

the period of the clock used for timed events in the FM erase algorithm. This register must be set with

appropriate values before the lockout sequence can begin. Refer to the JTAG section of the 56F8300

Peripheral User Manual for more details on setting this register value.

The value of the JTAG FM_CLKDIV[6:0] will replace the value of the FM register FMCLKD that divides

down the system clock for timed events, as illustrated in Figure 7-1. FM_CLKDIV[6] will map to the

PRDIV8 bit, and FM_CLKDIV[5:0] will map to the DIV[5:0] bits. The combination of PRDIV8 and DIV

must divide the FM input clock down to a frequency of 150kHz-200kHz. The “Writing the FMCLKD

equations for calculating the correct values.

56F8366 Datasheet(PDF) 135 Page - Freescale Semiconductor, Inc