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56F8366 Datasheet(PDF) 161 Page - Freescale Semiconductor, Inc |
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56F8366 Datasheet(HTML) 161 Page - Freescale Semiconductor, Inc |
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161 / 184 page ![]() Quad Timer Timing 56F8366 Technical Data, Rev. 6 Freescale Semiconductor 161 Preliminary Figure 10-13 SPI Slave Timing (CPHA = 1) 10.11 Quad Timer Timing Table 10-19 Timer Timing1, 2 1. In the formulas listed, T = the clock cycle. For 60MHz operation, T = 16.67ns. 2. Parameters listed are guaranteed by design. Characteristic Symbol Min Max Unit See Figure Timer input period PIN 2T + 6 — ns 10-14 Timer input high / low period PINHL 1T + 3 — ns 10-14 Timer output period POUT 1T - 3 — ns 10-14 Timer output high / low period POUTHL 0.5T - 3 — ns 10-14 SCLK (CPOL = 0) (Input) SCLK (CPOL = 1) (Input) MISO (Output) MOSI (Input) Slave MSB out Bits 14–1 tC tCL tCL tCH tDI MSB in Bits 14–1 LSB in SS (Input) tCH tDH tF tR Slave LSB out tD tA tELD tDV tF tR tELG tDV tDS |
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