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56F8366 Datasheet(PDF) 164 Page - Freescale Semiconductor, Inc |
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56F8366 Datasheet(HTML) 164 Page - Freescale Semiconductor, Inc |
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164 / 184 page  56F8366 Technical Data, Rev. 6 164 Freescale Semiconductor Preliminary Figure 10-18 Bus Wake Up Detection 10.15 JTAG Timing Figure 10-19 Test Clock Input Timing Diagram Table 10-23 JTAG Timing Characteristic Symbol Min Max Unit See Figure TCK frequency of operation using EOnCE1 1. TCK frequency of operation must be less than 1/8 the processor rate. fOP DC SYS_CLK/8 MHz 10-19 TCK frequency of operation not using EOnCE1 fOP DC SYS_CLK/4 MHz 10-19 TCK clock pulse width tPW 50 — ns 10-19 TMS, TDI data set-up time tDS 5— ns 10-20 TMS, TDI data hold time tDH 5— ns 10-20 TCK low to TDO data valid tDV —30 ns 10-20 TCK low to TDO tri-state tTS —30 ns 10-20 TRST assertion time tTRST 2T2 2. T = processor clock period (nominally 1/60MHz) —ns 10-21 T WAKEUP CAN_RX CAN receive data pin (Input) TCK (Input) VM VIL VM = VIL + (VIH – VIL)/2 tPW 1/fOP tPW VM VIH |
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