33797 datasheet(29/34 Pages) FREESCALE

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Analog Integrated Circuit Device Data

Freescale Semiconductor

33797

FUNCTIONAL DEVICE OPERATION

PROTECTION AND DIAGNOSIS FEATURES

SQUIB RESISTANCE DIAGNOSTIC DATA

RESULTS

A comparator result bit set to “1” indicates that the input

voltage is above the threshold resistance for that bit. Thus an

open squib would cause all bits to be set to “1”; likewise, a

shorted squib will cause all bits to be set to “0”.

Squib resistance tests are disabled during firing.

SQUIB DIAGNOSTICS SHORTS BETWEEN SQUIB

LINES (FIRING LOOPS) ($EX COMMAND)

This function monitors conditions that have shorts

between squib lines (firing loops). When enabled, a 2.7 mA

current source located in the SQB_HI_XX pin is activated

sourcing current from the selected SQB_HI_XX to the

SENSE_XX pin. The resulting voltage is checked on all other

squib lines to determine if the squib lines are shorted. In

applications using more than one squib driver IC, a separate

command can also be issued to check all squibs for shorted

squib lines.

SQUIB DIAGNOSTICS SHORTS BETWEEN SQUIB

LINES DIAGNOSTIC DATA RESULTS (SHORTS

BETWEEN FIRING LOOPS)

A comparator result bit set to “1” for SQUIB_XX indicates

standard test current detected in squib line under test.

A comparator result bit set to “0” for SQUIB_XX indicates

faulty diagnostic current detected in squib line under test.

A comparator result bit set to “1” for SQUIB_XX_SSQB_ YY

indicates that the squib line is shorted to the squib under test.

A comparator result bit set to “0” for SQUIB_XX_SSQB_YY

indicates no shorted squib line detected (standard

conditions). If more than two squibs are shorted together, the

response will consist of all “0”s.

RESET (RST)

The Reset pin has an internal current pull-down of typically

µA. While this pin is low, the internal functions of the squib

driver IC are disabled and all data in the serial interface shift

registers is cleared. This includes all FEN 1 and 2 counter

programming, squib driver activation, and squib driver FET

tests. With a minimum system VDD ≤ 4.1 V, the system reset

bar threshold will be set to “0”.

FEN_1 and FEN_2 (FEN) ($C8 COMMAND)

FEN_1 and FEN_2 have an internal current pull-down of

typically 40

µA. While the FEN pin is low, firing of the FET

drivers is disabled. All internal diagnostic functions and

results will be available through the serial interface. The FEN

pin must be pulled high to enable firing of the FET drivers.

Also, the pin state can be used to turn the FET driver “ON”

and “OFF” after the arm and fire command has been issued.

(That is, once the FET drivers are turned on, pulling FEN_1

or FEN_2 low can turn the drivers off if the latch and hold

function is not active, and pulling FEN_1 or FEN_2 high will

activate the drivers if the fire command is still active). Status

of FEN 1 and FEN 2 is contained in the C8 diagnostic byte,

as shown in Table 7, Diagnostic Bit Definitions, page 23.)

The FEN_1 and FEN_2 function should be capable of

latching and holding the enable function for electronic safing

function input. This function is required for dual-stage air bag

applications. FEN_1 or FEN_2 will be considered active

when either pin is active (“1”) for more than 12 ms. Tolerance

range for the filter to be used will be 12 to 16

µs.

When FEN_1 or FEN_2 input is active high, the FEN_1 or

FEN_2 function will be active high. When the FEN_1 or

FEN_2 input state transitions from high to low, a

programmable latching function will hold the FEN function

active until the timeout of the FEN timer. The programmable

latch and hold function will be capable of delays from 1.0 ms

to 255 ms, in 1.0 ms increments. The timer is reset to

programmed time when FEN_1 or FEN_2 pin transitions from

“0” to “1”. The programmable counter delay will be set

through an SPI command during module power-up/prove-

out. The default for the counter will be 0 ms.

The bits FEN 1 and FEN 2 STATUS are a reflection of

their respective pins.

The counter will be reset to 0-Sec time during a reset

condition.

Notes

1. Status information will be required to read counter-

programmed value.

2. Precautions need to be taken in the design to prevent

the latching function from becoming a glitch catching

function.

FEN 1 and FEN 2 COUNTER PROGRAMMING ($80

and $81 COMMAND)

The FEN 1 and FEN 2 counters require two separate 8-bit

writes be made to the shift register. The first write is to unlock

($80 or $81) and reset the FEN counter registers in

preparation of receiving a command. The second byte

contains the programming information to set the required

counter delay time (0 ms to 255 ms with 1.0 ms interval).

Squib IC Power-Up default and $80 or $81 followed by $00

command will set the counter to 0 ms timer delay (refer to

Table 8, page 24.)

The FEN 1 and FEN 2 Counter programming status bits

are a reflection of the counters programming. The

programming status information can be compared to the data

sent to ensure the squib driver was programmed properly.

Counter programming status will be shifted from the shift

unlock commands will be echoed back on the SPI Data

output.

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