XRT83SL38IB datasheet(18/88 Pages) EXAR

18 / 88 page

XRT83SL38

OCTAL T1/E1/J1 SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR

REV. 1.0.2

CLKSEL0

CLKSEL1

CLKSEL2

Clock Select inputs for Master Clock Synthesizer - Hardware mode

CLKSEL[2:0] are input signals to a programmable frequency synthesizer that can be

used to generate a master clock from an external accurate clock source according to

the table below.

In Hardware mode, the MCLKRATE control signal is generated from the state of

EQC[4:0] inputs.

In Host mode, the state of these pins are ignored and the master frequency PLL is con-

trolled by the corresponding interface bits. See

Table 36 register address 10000001

NOTE: These pins are internally pulled “Low” with a 50k

Ω resistor.

SIGNAL

NAME

LEAD #TYPE

DESCRIPTION

204 8

154 4

MCLK E1

kH z

128

256

128

2048

1544

M C LKT1

kH z

1544

2 048

1 544

2 048

CLKOUT/

kH z

1 544

2 048

1 544

2 048

1 544

2 048

1 544

2 048

1 544

2 048

1 544

2 048

1 544

CLKS EL0

CLKSEL1

CLK SEL2

154 4

204 8

2 048

1 544

M C LKR ATE

XRT83SL38IB Datasheet(PDF) 18 Page - Exar Corporation

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