XRT83SL38IB datasheet(72/88 Pages) EXAR

72 / 88 page

XRT83SL38

OCTAL T1/E1/J1 SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR

REV. 1.0.2

EXLOS

Extended LOS:

Writing a “1” to this bit extends the number of

zeros at the receive input of each channel before RLOS is

declared to 4096 bits. Writing a “0” reverts to the normal mode

(175+75 bits for T1 and 32 bits for E1).

R/W

ICT

In-Circuit-Testing:

Writing a “1” to this bit configures all the

output pins of the chip in high impedance mode for In-Circuit-

Testing. Setting the ICT bit to “1” is equivalent to connecting

the Hardware ICT pin 88 to ground.

R/W

TABLE 37: MICROPROCESSOR REGISTER #130, BIT DESCRIPTION

10000010

NAME

FUNCTION

TYPE

RESET

VALUE

BIT #

TXONCNTL

Transmit On Control:

In Host mode, setting this bit to “1” transfers the control of the

Transmit On/Off function to the TXON_n Hardware control

pins.

NOTE: This provides a faster On/Off capability for redundancy

application.

R/W

TERCNTL

Termination Control.

In Host mode, setting this bit to “1” transfers the control of the

RXTSEL to the RXTSEL Hardware control pin.

NOTE: This provides a faster On/Off capability for redundancy

application.

R/W

D5-D4

Reserved

TABLE 36: MICROPROCESSOR REGISTER #129, BIT DESCRIPTION

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