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XRT83SL38IB Datasheet(PDF) 47 Page - Exar Corporation |
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XRT83SL38IB Datasheet(HTML) 47 Page - Exar Corporation |
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47 / 88 page  XRT83SL38 45 REV. 1.0.2 OCTAL T1/E1/J1 SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR DUAL LOOP-BACK Figure 21 depicts the data flow in dual-loopback. In this mode, selecting the jitter attenuator in the transmit path will have the same result as placing the jitter attenuator in the receive path. In dual Loop-Back mode the recovered clock and data from the line are looped back through the transmitter to the TTIP and TRING without passing through the jitter attenuator. The transmit clock and data are looped back through the jitter attenuator to the RCLK and RPOS/RDATA and RNEG pins. FIGURE 21. SIGNAL FLOW IN DUAL LOOP-BACK MODE Tx Decoder Timing Control Rx Data & Clock Recovery JA TPOS TNEG TCLK RCLK RPOS RNEG Encoder TTIP TRING RTIP RRING |
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